A novel DFT technique for testing complete sets of ADCs and DACs in complex SiPs

IEEE Design and Test of Computers

Volumn 23, Issue 3, 2006, Pages 234-243

  Kerzérho, Vincent ^a,b,c   Cauvet, Philippe ^a   Bernard, Serge ^c   Azaïs, Florence ^a   Comte, Marianne ^b,c   Renovell, Michel ^b,c  

^a PHILIPS RESEARCH LABORATORIES   (Germany)

^b UNIV MONTPELLIER   (France)

^c LIRMM   (France)

Author keywords

[No Author keywords available]

Indexed keywords

COST EFFECTIVENESS; ELECTRONICS INDUSTRY; INTEGRATED CIRCUIT TESTING; PRODUCT DESIGN;

MIXED-SIGNAL CIRCUIT; SEMICONDUCTOR INDUSTRY;

CHIP SCALE PACKAGES;

EID: 33744534029     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2006.59     Document Type: Article

References (13)

1. M. Toner and G. Roberts, "A BIST Technique For a Frequency Response and Intermodulation Distortion Test of a Sigma-Delta ADC," Proc. IEEE VLSI Test Symp. (VTS 94), IEEE CS Press, 1994, pp. 60-65.
2. S.K. Sunter and N. Nagi, "A Simplified Polynomial-Fitting Algorithm for DAC and ADC BIST," Proc. Int'l Test Conf. (ITC 97), IEEE CS Press, pp. 389-395.
3. F. Azais et al., "Implementation of a Linear Histogram BIST for ADCs," Proc. Design Automation and Test in Europe (DATE 01), IEEE CS Press, pp. 590-595.
4. K. Arabi, B. Kaminska, and J. Rzeszut, "A New Built-In Self Test Approach for Digital-to-Analog and Analog-to-Digital Converters," Proc. IEEE Int'l Conf. Computer-Aided Design (ICCAD 94), IEEE Press, pp. 491-494.
5. N. Nagi, A. Chatterjee, and J. Abraham, "A Signature Analyzer for Analog and Mixed-Signal Circuits," Proc. IEEE Int'l Conf. Computer-Aided Design (ICCAD 94), IEEE Press, pp. 284-287.
6. M. Mahoney, DSP-Based Testing of Analog and Mixed-Signal Circuits, IEEE CS Press, 1987.
7. M. Burns and G.W. Roberts, An Introduction to Mixed-Signal IC Test and Measurement, Oxford Univ. Press, 2001.
8. J.L. Huertas, Test and Design-for-Testability in Mixed-Signal Integrated Circuits, Kluwer Academic Publishers, 2004.
9. J.A. Mielke, "Frequency Domain Testing of ADCs," IEEE Design & Test of Computers, vol. 13, no. 1, Spring 1996, pp. 64-69.
10. J.-M. Janik, "Estimation of A/D Converter Nonlinearities from Complex Spectrum," Proc. 8th Int'l Workshop ADC Modeling and Testing, 2003, pp. 8-10; also to be published in IEEE Trans. Instrumentation and Measurement.
11. H. Jiang, D. Chen, and R.L. Geiger, "Dither Incorporated Deterministic Dynamic Element Matching for High Resolution ADC Test Using Extremely Low Resolution DACs," Proc. IEEE Int'l Symp. Circuits and Systems (ISCAS 05), IEEE Press, 2005, pp. 4285-4288.
12. J.-M. Janik, D. Bloyet, and B. Guyot, "Measurement of Timing Jitter Contributions in a Dynamic Test Setup for A/D Converters," IEEE Trans. Instrumentation and Measurement, vol. 50, no. 3, June 2001, pp. 786-791.
13. F. Adamo et al., "FFT Test of A/D Converters to Determine the Integral Nonlinearity," IEEE Trans. Instrumentation and Measurement, vol. 51, no. 5, Oct. 2002, pp. 1050-1054.