Considering circuit observability don't cares in CNF satisfiability

Proceedings -Design, Automation and Test in Europe, DATE '05

Volumn II, Issue , 2005, Pages 1108-1113

  Fu, Zhaohui ^a,b   Yu, Yinlei ^a   Malik, Sharad ^a  

^a Princeton University   (United States)

^b NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN ALGEBRA; CONSTRAINT THEORY; FORMAL LOGIC; PROBLEM SOLVING;

BOOLEAN CONSTRAINT PROPAGATION (BCP); CONJUNCTIVE NORMAL FORM (CNF); LOGIC SYNTHESIS; SAT SOLVER;

NETWORKS (CIRCUITS);

EID: 33646943512     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2005.102     Document Type: Conference Paper

References (13)

1. K. Bartlett. R. K. Brayton, G. Hachtel, R. M. Jacoby, C. R. Morisson, R. L. Rudell, A. Sangiovanni-Vincentelli, and A. R. Wang. Multilevel logic optimization using implicit don't cares, IEEE Transactions on Computer-Aided Design, pages 723-740, June, 1988.
2. D. Brand. Verification of large synthesized designs. In Digest of Technical Papers of the IEEE International Conference on Computer-Aided Design, Santa Clara, CA, Novemeber, 1993.
3. F. Brglez and H. Fujiwara, A neutral netlist of 10 combinational benchmark circuits and a target translator in Fortran. In Special Session on ATPG and Fault Simulation, International Symposium on Circuits and Systems, June, 1985.
4. F. Corno, M. S. Reorda, and G. Squillero. RT-Level ITC 99 benchmarks and first ATPG results. In IEEE Design and Test of Computers, pages 44-53, July-August, 2000.
5. DIMACS. Satisfiability suggested format, available from ftp://dimacs.rutgers.edu/pub/challenge/ satisfiability/doc/satformat. tex, May, 1993.
6. M. K. Ganai, L. Zhang, P. Ashar, A. Gupta, and S. Malik. Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver. In 39th Design Automation Conference, June, 2002.
7. A. Gupta, A. Gupta, Z. Yang, and P. Ashar. Dynamic detection and removal of inactive clauses in SAT with application in image computation. In 38th Design Automation Conference, June, 2001.
8. A. Kuehlmann, M. K. Ganai, and V. Paruthi. Circuit-based Boolean reasoning. In 38th Design Automation Conference, June, 2001.
9. F. Lu. L.-C. Wang, K.-T. T. Cheng. J. Moondanos, and Z. Hanna. A signal correlation guided ATPG solver and its applications for solving difficult industrial cases. In 40th Design Automation Conference, June, 2003.
10. M. W. Moskewiez, C. F. Madigan, Y. Zhao, L. Zhang, and S. Malik. Chaff: Engineering an efficient SAT solver. In 39th Design Automation Conference, Las Vegas, June, 2001.
11. S. Safarpour, A. Veneris, R. Drechsler, and J. Lee. Managing don't cares in Boolean satisfiability. In Design Automation and Test in Europe, Paris, France, March, 2004.
12. G. S. Tseitin. On the complexity of derivation in prepositional calculus. Studies in Constructive Mathematics and Mathematical Logic, pages 115-125, 1968.
13. M. N. Velev. Encoding global unobservability for efficient translation to SAT. In The Seventh International Conference on Theory and Applications of Satisfiability Testing, Vancover, Canada, May, 2004.