Refinement maps for efficient verification of processor models

Proceedings -Design, Automation and Test in Europe, DATE '05

Volumn II, Issue , 2005, Pages 1304-1309

  Manolios, Panagiotis ^a   Srinivasan, Sudarshan K ^b  

^a Georgia Institute of Technology   (United States)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

PIPELINED MACHINE VERIFICATION; REFINEMENT MAPS;

DECISION MAKING; MATHEMATICAL MODELS; PIPELINE PROCESSING SYSTEMS;

PROGRAM PROCESSORS;

EID: 33646909906     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2005.257     Document Type: Conference Paper

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