Recent extensions to the SimpleScalar Tool suite

Performance Evaluation Review

Volumn 31, Issue 4, 2004, Pages 4-7

  Burger, Doug ^a   Austin, Todd M ^a   Keckler, Stephen W ^b  

^a UNIVERSITY OF MICHIGAN   (United States)

^b University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER GRAPHICS; COMPUTER OPERATING SYSTEMS; COMPUTER SIMULATION; EMBEDDED SYSTEMS; MATHEMATICAL MODELS; MULTIPROCESSING PROGRAMS;

GRAPHICAL SUPPORT; ISA-SPECIFIC SYSTEMS;

COMPUTER ARCHITECTURE;

EID: 33645687046     PISSN: 01635999     EISSN: 01635999     Source Type: Conference Proceeding    
DOI: 10.1145/1054907.1054909     Document Type: Conference Paper

References (9)

1. T. Austin, E. Larson, and D. Ernst. Simplescalar: An infrastructure for computer system modeling. IEEE Computer, 35(2), February 2002.
2. D. Burger, A. Kägi, and M. Hrishikesh. Memory hierarchy extensions to the simplescalar tool set. Technical Report TR-99-25, Department of Computer Sciences, University of Texas at Austin, Austin, TX, December 1999.
3. D. Burger and T. Austin. The simplescalar tool set version 2.0. Technical Report 1342, Computer Sciences Department, University of Wisconsin, Madison, WI, June 1997.
4. R. Desikan, D. Burger, and S. Keckler. Measuring experimental error in microprocessor simulation. In Proceedings of the 28th Annual International Symposium on Computer Architecture, pages 266-277, July 2001.
5. R. Desikan, D. Burger, S. Keckler, and T. Austin. Simalpha: a validated, execution-driven alpha 21264 simulator. Technical Report TR-00-04, Department of Computer Sciences, University of Texas at Austin, Austin, TX, February 2000.
6. E. Larson, S. Chatterjee, and T. Austin. The mase microarchitecture simulation environment. In Proceedings of the 2001 International Symposium on Performance Analysis of Systems and Software, June 2001.
7. K. Sankaralingam, R. Nagarajan, S. Keckler, and D. Burger. Simplescalar simulation of the powerpc instruction set architecture. Technical Report TR-01-23, Department of Computer Sciences, University of Texas at Austin, Austin, TX, February 2001.
8. G. S. Sohi. Instruction issue logic for high-performance, interruptible, multiple functional unit, pipelined computers. IEEE Trans. Comput., 39(3):349-359, March 1990.
9. C. Weaver, K. C. Barr, E. D. Marsman, D. Ernst, and T. Austin. Performance analysis using pipeline visualization. In Proceedings of the 2001 International Symposium on Performance Analysis of Systems and Software, June 2001.