Performance analysis using pipeline visualization

2001 IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2001

Volumn , Issue , 2001, Pages 18-21

  Weaver, Chris ^a   Barr, Kenneth C ^a   Marsman, Eric ^a   Ernst, Dan ^a   Austin, Todd ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ECONOMIC AND SOCIAL EFFECTS; PIPELINES;

ARCHITECTURAL MODIFICATION; ARCHITECTURAL SIMULATORS; CROSS-PLATFORM; HIGH-END MICROPROCESSORS; PERFORMANCE ANALYSIS; PROCESSOR PIPELINES; PROGRAM PERFORMANCE; SOFTWARE PROCESSOR;

PIPELINE PROCESSING SYSTEMS;

EID: 84937496563     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISPASS.2001.990670     Document Type: Conference Paper

References (19)

1. Intel. VTune: Visual Tuning Environment, 1997. http://developer.intel.com/design/perftool/vtune/index.htm.
2. DLXView.[online] Available: 'http://yara.ecn.purdue.edu/~teamaaa/dlxview/', cited June 2001.
3. J.L. Hennessy and D.A. Patterson, "Computer Architecture: A Quantitative Approach," Morgan Kaufmann, San Francisco, CA, 1996.
4. A.R. Lebeck, "Cache Conscious Programming in Undergraduate Cmputer Science," ACEM SIGCSE Technical Symposium on Computer Science Education, SIGCSE '99.
5. A.R. Lebeck and David A. Wood, "Cache Profiling and the SPEC Benchmarks: A Case Study," IEEE COMPUTER, 27(10):15-26, October 1994.
6. Robert Bosch, Chris Stolte, Gordon Stoll, Mendel Rosenblum and Pat Hanrahan,"Performance Analysis and Visualization of Parallel Systems Using SimOS and Rivet: A Case Study,"Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, January 2000.
7. Robert Bosch, Chris Stolte, Diane Tang, John Gerth, Mendel Rosenblum, and Pat Hanrahan,"Rivet: A Flexible Environment for Computer Systems Visualization," Computer Graphics 34(1), February 2000.
8. Chris Stolte, Robert Bosch, Pat Hanrahan, and Mendel Rosenblum,"Visualizing Application Behavior on Superscalar Processors,"In Proceedings of the Fifth IEEE Symposium on Information Visualization, October 1999.
9. J. Reilly, "SPEC Describes SPEC95 Products and Benchmarks," SPEC Newsletter, September 1995.
10. "Standard Performance Evaluation Corporation (SPEC2000 CPU benchmark)". Accessible on the Internet at World Wide Web URL http://www.spec.org/osg/cpu2000/.
11. B. Case. "SPEC2000 Retires SPEC92," The Microprocessor Report, vol. 9, 1995.
12. C. Lee, M. Potkonjak, and W. H. Mangione-Smith. "MediaBench: A tool for evaluating and synthesizing multimedia and communications systems," In Proceedings of the International Symposium on Microarchitecture, pages 330-5, December 1997
13. RSA Security. "RC6," http://csrc.nist.gov/encryption/aes/round2/AESAlgs/RC6, August 1999.
14. Intel Corporation, "SA-110 Microprocessor Technical Reference Manual," ftp://download.intel.com/designstrong/manuals/27805801.pdf.
15. Intel Corporation, "Intel StrongARM SA-110 Microprocessors Instruction Timing," ftp://download.in-tel.com/design/strong/applnots/27819401.pdf.
16. Rebel.com NetWinder Family, http://www.rebel.com/netwinder.
17. D. Kirovski, J. Kin and W. H. Mangione-Smith. "Procedure Based Program Compression," Proceedings of the 30th Annual International Symposium on Microarchitecture, December 1997.CPROF paper
18. Doug Burger, Todd M. Austin and Steve Bennett. "Evaluating Future Microprocessors: The SimpleScalar ToolSet". University of Wisconsin-Madison. Computer Sciencies Department. Technical Report CS-TR-1308, July 1996.
19. C. Weaver, K. Barr, E. Marsman, D. Ernst, and T. Austin. "Performance Analysis Using Pipeline Visualization". http://www.eecs.umich.edu/~taustin/papers/gpvtech.pdf