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Volumn 16, Issue 4, 2006, Pages 188-190

A 4-mW monolithic CMOS LNA at 5.7 GHz with the gate resistance used for input matching

Author keywords

CMOS; Effective transconductance; Inductive degeneration; Input matching; Low noise amplifier

Indexed keywords

EFFECTIVE TRANSCONDUCTANCE; INDUCTIVE DEGENERATION; INPUT MATCHING; LOW-NOISE AMPLIFIER (LNA);

EID: 33645653059     PISSN: 15311309     EISSN: None     Source Type: Journal    
DOI: 10.1109/LMWC.2006.872128     Document Type: Article
Times cited : (50)

References (7)
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  • 2
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    • Dec.
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  • 3
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    • Apr.
    • C.-Y. Cha and S.-G. Lee, "A 5.2 GHz LNA in 0.35 μm CMOS utilizing inter-stage series resonance and optimizing the substrate resistance," IEEE J. Solid-State Circuits, vol. 38, no. 4, pp. 669-672, Apr. 2003.
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  • 4
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    • Y. Cheng, M. J. Deen, and C.-H. Chen, "MOSFET modeling for RFIC design," IEEE Trans. Electron Devices, vol. 52, no. 7, pp. 1286-1303, Jul. 2005.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.