Investigation of back gate interface states by drain current hysteresis in PD-SOI n-MOSFETs

Physica B: Condensed Matter

Volumn 376-377, Issue 1, 2006, Pages 416-419

  Hayama, K ^a   Takakura, K ^a   Okada, S ^a   Kudou, T ^a   Ohyama, H ^a   Rafi J M ^b   Martino, J A ^c   Mercha, A ^d   Simoen, E ^d   Claeys, C ^d,e  

^a KUMAMOTO NATIONAL COLLEGE OF TECHNOLOGY   (Japan)

^b INSTITUTO DE MICROELECTRÓNICA DE BARCELONA   (Spain)

^c UNIVERSITY OF SÃO PAULO   (Brazil)

^d IMEC   (Belgium)

^e UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

Hysteresis; Interface states; PD SOI MOSFET; Temperature dependence

Indexed keywords

ACTIVATION ENERGY; ELECTRIC CURRENTS; HYSTERESIS; TEMPERATURE;

BACK GATE VOLTAGES (VBG);

MOSFET DEVICES;

EID: 33645138828     PISSN: 09214526     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.physb.2005.12.107     Document Type: Conference Paper

References (5)

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3. J. Pretet, T. Matsumoto, T. Poiroux, S. Cristoloveanu, R. Gwoziecki, C. Raynaud, A. Roveda, and H. Brut Proc. ESSDERC 2002 515
4. K. Hayama Linear kink effect induced drain current hysteresis in ultra thin gate oxide FD-SOI n-MOSFETs Proceedings of ULIS 2004 Leuven, Belgium 2004 59 62
5. K. Hayama, K. Takakura, H. Ohyama, J.M. Rafí, A. Mercha, E. Simoen, and C. Claeys J. Mater. Sci. Mater. Electron. 16 2005 459