Body potential analysis of ultra thin gate oxide FD-SOI MOSFETs in accumulation mode operation

Journal of Materials Science: Materials in Electronics

Volumn 16, Issue 7, 2005, Pages 459-462

  Hayama, K ^a   Takakura, K ^a   Ohyama, H ^a   Rafi J M ^b   Mercha, A ^c   Simoen, E ^c   Claeys, C ^c,d  

^a KUMAMOTO NATIONAL COLLEGE OF TECHNOLOGY   (Japan)

^b INSTITUTO DE MICROELECTRÓNICA DE BARCELONA   (Spain)

^c IMEC   (Belgium)

^d UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

CURRENT VOLTAGE CHARACTERISTICS; ELECTRIC POTENTIAL; ELECTRON ENERGY LEVELS; ELECTRON TUNNELING; GATES (TRANSISTOR); IMPACT IONIZATION; SILICON ON INSULATOR TECHNOLOGY; TRANSCONDUCTANCE;

ACCUMULATION MODE OPERATION; BACK GATE VOLTAGE; BODY POTENTIAL ANALYSIS; DRAIN VOLTAGE; ELECTRON VALENCE BAND GATE TUNNELING; FULLY-DEPLETED SILICON-ON-INSULATOR; GATE LENGTH; ULTRA THIN GATE OXIDE;

MOSFET DEVICES;

EID: 24944476447     PISSN: 09574522     EISSN: None     Source Type: Journal    
DOI: 10.1007/s10854-005-2315-3     Document Type: Article

References (6)

1. T. Skotnicki, G. Merckel and A. Merrachi, in IEDM Technical Digest (1989) p. 87.
2. M. V. Fischetti and S. E. Laux, in IEDM Technical Digest (1995) p. 305.
3. A. Mercha, J. M. Rafí E. Simoen, E. Augendre and C. Claeys, IEEE Trans. Electron Dev. 50 (7) (2003) 1675. 10.1109/TED.2003.814983
4. J. Pretet, T. Matsumoto, T. Poiroux, S. Cristoloveanu, R. Gwoziecki, C. Raynaud, A. Roveda and H. Brut, in Proc. of ESSDERC, Italy (2002) p. 515.
5. K. Hayama, H. Ohyama, J. M. Rafí, A. Mercha, E. Simoen and C. Claeys, "Linear Kink Effect" Induced Drain Current Hysteresis in Ultra Thin Gate Oxide FD-SOI n -MOSFETs, in: Proc. ULIS 2004, Leuven, Belgium, Ed. K. De Meyer and N. Collaert (2004) 59.
6. J.P. Colinge, "Silicon-On-Insulator Technology: Materials to VLSI," 2nd ed. (Kluwer Academic Publishers, 1997).