Impact of CMP-induced topography on a 65nm technology copper damascene interconnect module

Advanced Metallization Conference (AMC)

Volumn , Issue , 2006, Pages 533-537

  Ramachandran, V ^a,e   Hagan, J A ^a   Hong, D H ^d   Jamin, F F ^a   Kaltalioglu, E ^c   Kim, S O ^c   Li, W K ^a   Marokkey, S ^c   Naujok, M ^c   Park, K C ^d   Siew, Y K ^b   Cowley, A P ^a  

^a IBM MICROELECTRONICS   (United States)

^b CHARTERED SEMICONDUCTOR MANUFACTURING LTD   (Singapore)

^c INFINEON TECHNOLOGIES AG   (Germany)

^d SAMSUNG Electronics   (South Korea)

^e NONE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHEMICAL MECHANICAL POLISHING; COPPER; METALLIZING; PHOTOLITHOGRAPHY; PLATING; CHIP SCALE PACKAGES; MATERIALS SCIENCE; SURFACE TOPOGRAPHY;

CMP-INDUCED TOPOGRAPHY; CU WIRING LAYERS; DAMASCENE INTERCONNECT MODULE; CHIP-TOPOGRAPHY; COPPER DAMASCENE INTERCONNECT MODULES; METAL PUDDLES;

NANOTECHNOLOGY; INTERCONNECTION NETWORKS;

EID: 33644933315     PISSN: 15401766     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. J. Cong et al, 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997. Digest of Technical Papers.
2. R. Tian et al, Transactions on Computer-Aided Design of Integrated Circuits and Systems, IEEE, Volume 20, Issue 7, July 2001 Page(s):902-910
3. S. Narinesingh et al, Devices, Proceedings of the Fourth IEEE International Caracas Conference on Circuits and Systems, 2002, 17-19 April 2002 Page(s):D033-1-D033-6
4. M. Pike et al,. IEEE Conference and Workshop Advanced Semiconductor Manufacturing, 2004. ASMC '04, Page(s):75-78
5. L. Economikos et al, Proceedings of the IEEE 2004 International Interconnect Technology Conference, 2004 Page(s):233-235