Logic synthesis for asynchronous circuits based on STG unfoldings and incremental SAT

Fundamenta Informaticae

Volumn 70, Issue 1-2, 2006, Pages 49-73

  Khomenko, Victor ^a   Koutny, MacIej ^a   Yakovlev, Alex ^a  

^a NEWCASTLE UNIVERSITY   (United Kingdom)

Author keywords

Asynchronous circuits; Automated synthesis; Incremental SAT; Logic synthesis; Net unfoldings; Partial order techniques; Petrinets; Self timed circuits; Signal transition graphs; STG

Indexed keywords

ALGORITHMS; GRAPH THEORY; LOGIC GATES; PETRI NETS; PROBLEM SOLVING; ASYNCHRONOUS SEQUENTIAL LOGIC; CODES (SYMBOLS); COMPUTER CIRCUITS; GRAPHIC METHODS; LOGIC SYNTHESIS; TIMING CIRCUITS;

ASYNCHRONOUS CIRCUITS; AUTOMATED SYNTHESIS; INCREMENTAL SAT; LOGIC SYNTHESIS; NET UNFOLDINGS; PARTIAL ORDER TECHNIQUES; SELF-TIMED CIRCUITS; SIGNAL TRANSITION GRAPHS; STG;

LOGIC CIRCUITS; PETRI NETS;

ASYNCHRONOUS CIRCUITS; AUTOMATED SYNTHESIS; INCREMENTAL SATISFIABILITY; NET UNFOLDING; PARTIAL ORDER TECHNIQUE.; PARTIAL ORDER TECHNIQUES; SELF-TIMED CIRCUITS; SIGNAL TRANSITION GRAPHS; UNFOLDINGS;

EID: 33244470373     PISSN: 01692968     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Conference Paper

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