A unified signal transition graph model for asynchronous control circuit synthesis

Formal Methods in System Design

Volumn 9, Issue 3, 1996, Pages 139-188

  Yakovlev, Alexandre ^a   Lavagno, Luciano ^b   Sangiovanni Vincentelli, Alberto ^c  

^a NEWCASTLE UNIVERSITY   (United Kingdom)

^b POLITECNICO DI TORINO   (Italy)

^c UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Asynchronous circuits; Concurrency; Delay models; Delay insensitivity; Hazards; Specification; Speed independence

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER SIMULATION; GRAPH THEORY; MATHEMATICAL MODELS;

ASYNCHRONOUS CIRCUITS; DELAY INSENSITIVITY; DELAY MODELS; SIGNAL TRANSITION GRAPH;

ELECTRIC NETWORK SYNTHESIS;

EID: 0030286197     PISSN: 09259856     EISSN: None     Source Type: Journal    
DOI: 10.1007/BF00122081     Document Type: Article

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