Probe module for wafer-level testing of gigascale chips with electrical and optical I/O interconnects

Proceedings of the ASME/Pacific Rim Technical Conference and Exhibition on Integration and Packaging of MEMS, NEMS, and Electronic Systems: Advances in Electronic Packaging 2005

Volumn PART B, Issue , 2005, Pages 1593-1599

  Thacker, Hiren ^a   Ogunsola, Oluwafemi ^a   Bakir, Muhannad ^a   Meindl, James ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FABRICATION; MICROELECTROMECHANICAL DEVICES; OPTICAL INTERCONNECTS; POLYMERS; SILICON WAFERS;

CHIP-TO-CHIP COMMUNICATIONS; MICRO-OPTO-ELECTRO-MECHANICAL-SYSTEMS(MOEMS); MICROFABRICATION TECHNIQUES;

MICROPROCESSOR CHIPS;

EID: 32844470247     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1115/ipack2005-73302     Document Type: Conference Paper

References (5)

1. D. Miller, "Rationale and challenges for optical interconnects to electronic chips," Proc. IEEE, vol. 88, pp. 728-749, June 2000.
2. M. Bakir, A. Mule', T. Gaylord, P. Kohl, K. Martin, and J. Meindl, "Sea of dual mode polymer pillar I/O interconnections for gigascale integration," in IEEE Int. Solid-State Circuits Conf., vol. vol.1, 2003, pp. 372-373.
3. Semiconductor Industry Association, "The International Technology Roadmap for Semiconductors," 2004.
4. "ABCs of probes," Primer, Tektronix.
5. M. Bakir and J. Meindl, "Sea of polymer pillars electrical and optical chip I/O interconnections for gigascale integration," IEEE Trans. on Electron Dev., vol. 51, no. 7, pp. 1069-1077, 2004.