Design and analysis of a self-timed duplex communication system

IEEE Transactions on Computers

Volumn 53, Issue 7, 2004, Pages 798-814

  Yakovlev, Alex ^a   Furber, Steve ^b   Krenz, René ^c   Bystrov, Alexandre ^a  

^a NEWCASTLE UNIVERSITY   (United Kingdom)

^b UNIVERSITY OF MANCHESTER   (United Kingdom)

^c IEEE   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

ASYNCHRONOUS SEQUENTIAL LOGIC; COMPUTER SIMULATION; MATHEMATICAL MODELS; NETWORK PROTOCOLS; PETRI NETS;

ASYNCHRONOUS COMMUNICATION SYSTEM; POWER AND PIN EFFICIENCY; SELF TIMED CIRCUITS; SIGNAL TRANSITION GRAPHS;

DATA COMMUNICATION SYSTEMS;

EID: 3242655678     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/TC.2004.26     Document Type: Article

References (23)

1. J. Bainbridge, Asynchronous System-on-Chip Interconnect. Springer-Verlag, 2002.
2. L. Benini and G. De Micheli, "Networks on Chips: A New SoC Paradigm," Computer, vol. 35, no. 1, pp. 70-78, Jan. 2002.
3. A. Bystrov and A. Yakovlev, "Asynchronous Circuit Synthesis by Direct Mapping: Interfacing to Environment," Proc. Eighth IEEE Int'l Symp. Asynchronous Circuits and Systems, pp. 127-136, 2002.
4. J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, and A. Yakovlev, Logic Synthesis of Asynchronous Controllers and Interfaces. Springer-Verlag, 2002.
5. A. Danthine, "Protocol Representation with Finite-State Models," IEEE Trans. Comm., vol. 28, no. 4, pp. 632-643, 1980.
6. R. David, "Modular Design of Asynchronous Circuits Defined by Graphs," IEEE Trans. Computers, vol. 26, no. 8, pp. 727-737, Aug. 1977.
7. A. Efthymiou, "The Design of a Low-Power Asynchronous Communication System," Proc. Ninth UK Asynchronous Forum, pp. 1-5, Dec. 2000.
8. R.M. Fuhrer, S.M. Nowick, M. Theobald, N.K. Jha, B. Lin, and L. Plana, "Minimalist: An Environment for the Synthesis, Verification, and Testability of Burst-Mode Asynchronous Machines," Technical Report TR CUCS-020-99, Columbia Univ., New York, July 1999.
9. S.B. Furber, A. Efthymiou, and M. Singh, "A Power-Efficient Duplex Communication System," Proc. Int'l Workshop Asynchronous Interfaces (AINT'2000), 2000.
10. L.A. Hollaar, "Direct Implementation of Asynchronous Control Units," IEEE Trans. Computers, vol. 31, no. 12, pp. 1133-1141, Dec. 1982.
11. A. Madalinski, A. Bystrov, V. Khomenko, and A. Yakovlev, "Visualization and Resolution of Coding Conflicts in Asynchronous Circuit Design," Proc. Design, Automation and Test in Europe Conf., pp. 926-931, Mar. 2003.
12. K.L. McMillan, Symbolic Model Checking. Kluwer AP, 1993.
13. T. Murata, "Petri Nets: Properties, Analysis and Applications," Proc. IEEE, vol. 77, no. 4, pp. 541-580, 1989.
14. S.M. Nowick, "Automatic Synthesis of Burst-Mode Asynchronous Controllers," PhD thesis, Dept. of Computer Science, Stanford Univ., 1993.
15. L.Y. Rosenblum and A.V. Yakovlev, "Signal Graphs: From Self-Timed to Timed Ones," Proc. Int'l Workshop Timed Petri Nets, pp. 199-207, July 1985.
16. A. Semenov "Verification and Synthesis of Asynchronous Control Circuits Using Petri Net Unfoldings," PhD thesis, Univ. of Newcastle upon Tyne, July 1997.
17. D. Sokolov, A. Bystrov, and A. Yakovlev, "STG Optimisation in the Direct Mapping of Asynchronous Circuits," Proc. Design, Automation and Test in Europe, pp. 932-937, Mar. 2003.
18. J.-T. Udding, "Classification and Composition of Delay-Insensitive Circuits," PhD thesis, Eindhoven Univ. of Technology, 1984.
19. K. vanBerkel, "Beware the Isochronic Fork," Integration, the VLSI J., vol. 13, no. 2, pp. 103-128, June 1992.
20. V.I. Varshavsky and V.B. Marakhovsky, "Asynchronous Control Device Design by Net Model Behavior Simulation," Application and Theory of Petri Nets 1996, J. Billington and W. Reisig, eds., June 1996.
21. T. Verhoeff, "Delay-Insensitive Codes - An Overview," Distributed Computing, vol. 3, no. 1, pp. 1-8, 1988.
22. A. Yakovlev, V. Varshavsky, V. Marakhovsky, and A. Semenov, "Designing an Asynchronous Pipeline Token Ring Interface," Proc. Int'l Conf. Asynchronous Design Methodologies, pp. 32-41, May 1995.
23. A.V. Yakovlev and A.M. Koelmans, "Petri Nets and Digital Hardware Design," Lectures on Petri Nets II: Applications. Advances in Petri Nets, W. Reisig and G. Rozenberg, eds., 1998.