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Volumn PV 2005-05, Issue , 2005, Pages 109-117
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High-K gate stack engineering - Towards meeting low standby power and high performance targets
a,b c,d,e,f,g a c c,d,e,f,g a a a,b a c,d,e,f,g c,d,e,f,g a c,d,e,f,g a a a a c,d,e,f,g a a more..
c
Freescale
*
e
Matsushita
(Japan)
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Author keywords
[No Author keywords available]
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Indexed keywords
CAPACITANCE ELECTRICAL THICKNESS (CET);
GATE STACK ENGINEERING;
LOW STANDBY POWER (LSTP);
CAPACITANCE;
GATES (TRANSISTOR);
DIELECTRIC MATERIALS;
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EID: 31944442762
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (3)
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References (18)
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