Yield analysis of logic circuits

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 2004, Pages 103-108

  Appello, D ^a   Fudoli, A ^a   Giarda, K ^a   Gizdarski, E ^b   Mathew, B ^b   Tancorre, V ^a  

^a STMICROELECTRONICS   (Italy)

^b SYNOPSYS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC TEST EQUIPMENT (ATE); SYSTEM ON CHIP (SOC); TEST VECTORS; YIELD ANALYSIS;

AUTOMATIC TESTING; CALCULATIONS; CMOS INTEGRATED CIRCUITS; DESIGN FOR TESTABILITY; DETECTOR CIRCUITS; MAPPING; PROGRAM DIAGNOSTICS; QUALITY CONTROL; SHIFT REGISTERS; YIELD STRESS;

LOGIC CIRCUITS;

EID: 3142713183     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VTEST.2004.1299232     Document Type: Conference Paper

References (12)

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