Debugging VHDL designs: Introducing multiple models and first empirical results

Applied Intelligence

Volumn 21, Issue 2 SPEC. ISS., 2004, Pages 159-172

  Wotawa, Franz ^a  

^a GRAZ UNIVERSITY OF TECHNOLOGY   (Austria)

Author keywords

Debugging hardware designs; Model based diagnosis; Modeling for diagnosis

Indexed keywords

COMPUTER HARDWARE; COMPUTER PROGRAMMING; COSTS; FAILURE ANALYSIS; HIERARCHICAL SYSTEMS; JAVA PROGRAMMING LANGUAGE; LOGIC DESIGN; MATHEMATICAL MODELS; PROBABILITY; SET THEORY;

DEBUGGING HARDWARE DESIGNS; MODEL-BASED DIAGNOSIS; MODELLING FOR DIAGNOSIS; STRUCTURAL FAULT;

PROGRAM DEBUGGING;

EID: 3142708059     PISSN: 0924669X     EISSN: None     Source Type: Journal    
DOI: 10.1023/B:APIN.0000033635.98612.1e     Document Type: Conference Paper

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