NBTI: A growing threat to device reliability

Semiconductor International

Volumn 27, Issue 3, 2004, Pages 47-54

  Peters, Laura ^a  

^a NONE

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COST EFFECTIVENESS; DIFFUSION IN SOLIDS; ELECTRIC CURRENTS; GATES (TRANSISTOR); MATHEMATICAL MODELS; RELAXATION PROCESSES; RELIABILITY; STRESSES; THRESHOLD VOLTAGE;

DRIVE CURRENTS; GATE THICKNESS; NEGATIVE BIAS TEMPERATURE INSTABILITY (NBTI); STRESS TESTING;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 3142556205     PISSN: 01633767     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Review

References (3)

1. M.A. Alam, "A Critical Examination of the Mechanics of Dynamic NBTI for PMOSFETs," IEEE Intl. Electron Devices Mtg., December 2003, p. 345.
2. G. Chen, et al., "Dynamic NBTI of PMOS Transistors and Its Impact on Device Lifetime," IEEE 41st Annual Intl. Reliability Physics Symp., April 2003, p. 196.
3. S. Rangan, N. Mielke and E. Yeh, "Universal Recovery Behavior of Negative Bias Temperature Instability," IEEE Intl. Electron Devices Mtg., December 2003, p. 341.