Timing analysis for preemptive multi-tasking real-time systems with caches

Proceedings - Design, Automation and Test in Europe Conference and Exhibition

Volumn 2, Issue , 2004, Pages 1034-1039

  Tan, Yudong ^a   Mooney III, Vincent J ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; INTEGER PROGRAMMING; LINEAR PROGRAMMING; MOBILE ROBOTS; MULTITASKING; PROGRAM PROCESSORS; ROBOT APPLICATIONS; ESTIMATION; EXHIBITIONS; REGRESSION ANALYSIS;

INTEGER LINEAR PROGRAMMING (ILP); TIMING ANALYSIS; WORST CASE EXECUTION TIME (WCET); WORST CASE RESPONSE TIME (WCRT);

REAL TIME SYSTEMS;

BEHAVIOR ANALYSIS; PATH ANALYSIS; SET ASSOCIATIVE CACHE; TIMING ANALYSIS; WORST CASE RESPONSE TIME;

EID: 3042660323     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

1. D. Kirk, "SMART (Strategic Memory Allocation for Real-Time) Cache Design", Proc. IEEE 10th Real-Time System Symposium, pp.229-237, December 1989.
2. G. Suh, L. Rudolph and S. Devadas, "Dynamic Cache Partitioning for Simultaneous Multithreading Systems," Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Systems, August, pp.116-127, September 2001.
3. I. Liedtke, H.Härtig and M. Hohmuth, "OS-Controlled Cache Predictability for Real-Time Systems," Proceedings of the Third IEEE Real-Time Technology and Applications Symposium (RTAS'97), pp. 213-227, June 1997.
4. F. Muller, "Compiler Support for Software-based Cache Partitioning," Proceedings of ACM SIGPLAN Workshop on Languages, Compilers and Tools for Real-Time Systems, pp. 125-133, June 1995.
5. Y. Li and S. Malik, Performance Analysis of Real-Time Embedded Software, Kluwer Academic Publishers, Boston, 1999.
6. F. Wolf, Behavioral Intervals in Embedded Software, Kluwer Academic Publishers, Norwell, MA, 2002.
7. J. Lehoczky, L. Sha and Y. Ding, "The Rate Monotonic Scheduling Algorithm:Exact Characterization and Average Case Behavior," Proc. IEEE 10th Real-Time System Symposium, pp. 166-171, 1989.
8. C. Liu and J. Layland, "Scheduling Algorithms for Multiprogramming in a Hard Real-Time Environment," Journal of ACM, Vol. 20, No. 1, pp. 26-61, January 1973.
9. K. Tindell, A. Burns, A. Wellings, "An Extendible Approach for Analyzing Fixed Priority Hard Real-Time Tasks," Real-Time Systems Vol.6, No.2, pp. 133-151, March 1994.
10. J. Busquets-Mataix, J. Serrano, R. Ors, P. Gil and A. Wellings, "Adding instruction cache effect to schedulability analysis of preemptive real-time systems," Real-Time Technology and Applications Symposium, pp. 204-212, June 1996.
11. C. Lee, J. Hahn, Y. Seo, S. Min, R. Ha, S. Hong, C. Park, M. Lee and C. Kim. "Analysis of Cache-related Preemption Delay in Fixed-priority Preemptive Scheduling," IEEE Transactions on Computers, Vol. 47, No. 6, pp. 700-713, 1998.
12. D. Sun, D. Blough and V. Mooney, "Atalanta: A New Multiprocessor RTOS Kernel for System-on-a-Chip Applications," Technical Report GIT-CC-02-19, Georgia Institute of Technology, April 2002.
13. Mentor Graphics, Seamless Hardware/Software Co-Verification, http://www.mentor.com/seamless/.
14. Mentor Graphics XRAY Debugger, http://www.mentor.com/embedded/xray/.