How can system level design solve the interconnect technology scaling problem?

Proceedings - Design, Automation and Test in Europe Conference and Exhibition

Volumn 1, Issue , 2004, Pages 332-337

  Catthoor, Francky ^a,b   Cuomo, Andrea ^c   Martin, Grant ^d   Groeneveld, Patrick ^e   Rudy, Lauwereins ^a,b   Maex, Karen ^a,b   Van De Steeg, Patrick ^f   Wilson, Ron ^g  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

^c STMICROELECTRONICS   (Italy)

^d CADENCE DESIGN SYSTEMS   (United States)

^e MAGMA DESIGN AUTOMATION   (United States)

^f NXP SEMICONDUCTORS   (Netherlands)

^g CMP Media   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT DESIGN; INTERCONNECT TECHNOLOGY; MOBILITY SUBSTRATES; IC MANUFACTURERS; INDUSTRIAL DESIGNERS; INTERCONNECT DELAY; PHYSICAL LIMITS; SEMICONDUCTOR TECHNOLOGY; SYSTEM DESIGNERS; SYSTEM LEVEL DESIGN;

COMPUTER AIDED DESIGN; DEGREES OF FREEDOM (MECHANICS); DIELECTRIC MATERIALS; ELECTRIC CONDUCTIVITY; ELECTRIC FIELD EFFECTS; ELECTRIC POTENTIAL; ELECTRIC POWER SYSTEMS; MICROPROCESSOR CHIPS; TRANSISTORS; DESIGN; EXHIBITIONS; MECHANICS; SEMICONDUCTOR DEVICE MANUFACTURE;

INTERCONNECTION NETWORKS; SYSTEMS ANALYSIS;

EID: 3042656852     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2004.1268869     Document Type: Conference Paper

References (7)

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