A low power strategy for future mobile terminals

Proceedings - Design, Automation and Test in Europe Conference and Exhibition

Volumn 1, Issue , 2004, Pages 702-703

  Nikitovic, Mladen ^a   Brorsson, Mats ^a  

^a ROYAL INSTITUTE OF TECHNOLOGY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP-MULTIPROCESSORS (CMP); DYNAMIC POWER CONSUMPTION; INSTRUCTION-LEVEL PARALLELISM (ILP); THREAD-LEVEL PARALLELISM (TLP); CHIP-MULTIPROCESSOR; MOBILE TERMINAL; POTENTIAL IMPACTS; POWER-AWARE SCHEDULING; SYSTEM CALLS; SYSTEM LEVELS; TOTAL ENERGY;

ALGORITHMS; COMPUTER ARCHITECTURE; ENERGY UTILIZATION; INTELLIGENT AGENTS; MOBILE COMPUTING; PERSONAL DIGITAL ASSISTANTS;

MULTIPROCESSING SYSTEMS; EXHIBITIONS;

EID: 3042561707     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2004.1268938     Document Type: Conference Paper

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