Evaluation of scheduling and allocation algorithms while mapping assembly code onto FPGAs

Proceedings of the ACM Great Lakes Symposium on VLSI

Volumn , Issue , 2004, Pages 397-400

  Zaretsky, David ^a   Mittal, Gaurav ^a   Tang, Xiaoyong ^a   Banerjee, Prith ^a  

^a Northwestern University   (United States)

Author keywords

Binary Translation; Chaining; Compilers; FPGAs; Hardware Synthesis; Optimizations; Scheduling

Indexed keywords

ALGORITHMS; COMPUTER HARDWARE; DIGITAL SIGNAL PROCESSING; MAPPING; OPTIMIZATION; PROGRAM COMPILERS; SCHEDULING;

BINARY TRANSLATION; CHAINING; COMPILERS; HARDWARE SYNTHESIS;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 2942668778     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/988952.989048     Document Type: Conference Paper

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