Narrow distribution of threshold voltage in 4-Mbit MONOS memory-cell array with F-N channel write and direct/F-N tunneling erase operation as a single transistor structure

IEEE Transactions on Electron Devices

Volumn 51, Issue 6, 2004, Pages 895-900

  Nakamura, Akihiro ^a   Moriya, Hiroyuki ^a   Terano, Toshio ^a   Kosaka, Hideo ^b   Hashiguchi, Akihiko ^b   Nomoto, Kazumasa ^b   Fujiwara, Ichiro ^a   Kobayashi, Toshio ^a   Oda, Tatsuji ^a  

^a SCSSNC   (Japan)

^b SONY CORPORATION   (Japan)

Author keywords

Fowler Nordheim (F N) tunneling; Low voltage operation; MONOS; ONO; Reliability; Tail bit

Indexed keywords

CAPACITANCE; ELECTRON TUNNELING; RELIABILITY; THRESHOLD VOLTAGE;

SINGLE TRANSISTOR STRUCTURE; TUNNELING ERASE OPERATION;

TRANSISTORS;

EID: 2942657421     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2004.827369     Document Type: Article

References (16)

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