MINFLOTRANSIT: min-cost flow based transistor sizing tool

Proceedings - Design Automation Conference

Volumn , Issue , 2000, Pages 649-654

  Sundararajan, Vijay ^a   Sapatnekar, Sachin S ^a   Parhi, Keshab K ^a  

^a UNIVERSITY OF MINNESOTA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMBINATORIAL CIRCUITS; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; COST EFFECTIVENESS; INTEGRATED CIRCUIT LAYOUT; ITERATIVE METHODS; OPTIMIZATION;

ITERATIVE RELAXATION; MINFLOTRANSIT; SIMPLE MONOTONIC PROGRAM; TRANSISTOR SIZE OPTIMIZATION PROBLEM; TRANSISTOR SIZING TOOL;

TRANSISTORS;

EID: 0033684206     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (16)