High-performance polycrystalline silicon thin-film transistor with multiple nanowire channels and lightly doped drain structure

Applied Physics Letters

Volumn 84, Issue 19, 2004, Pages 3822-3824

  Wu, Yung Chun ^a   Chang, Ting Chang ^b   Chang, Chun Yen ^a   Chen, Chi Shen ^a   Tu, Chun Hao ^a   Liu, Po Tsun ^c   Zan, Hsiao Wen ^a   Tai, Ya Hsiang ^a  

^a NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^b NATIONAL SUN YAT SEN UNIVERSITY   (Taiwan)

^c NATIONAL NANO DEVICE LABORATORIES   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CHEMICAL VAPOR DEPOSITION; CRYSTALLIZATION; DOPING (ADDITIVES); ELECTRIC FIELD EFFECTS; GRAIN BOUNDARIES; LEAKAGE CURRENTS; LIQUID CRYSTAL DISPLAYS; METALLIZING; NANOSTRUCTURED MATERIALS; PASSIVATION; POLYSILICON; RAPID THERMAL ANNEALING; SCANNING ELECTRON MICROSCOPY; SILICON WAFERS; TRANSMISSION ELECTRON MICROSCOPY;

GATE VOLTAGE; LIGHT DOPED DRAIN (LDD); MULTIPLE NANOWIRE CHANNELS (MNC); PLASMA PASSIVATION;

THIN FILM TRANSISTORS;

EID: 2942578186     PISSN: 00036951     EISSN: None     Source Type: Journal    
DOI: 10.1063/1.1745104     Document Type: Article

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