A unified framework for generating all propagation functions for logic errors and events

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 23, Issue 6, 2004, Pages 980-986

  Michael, Maria K ^a   Haniotakis, Themistoklis ^b   Tragoudas, Spyros ^b  

^a UNIVERSITY OF CYPRUS   (Cyprus)

^b Southern Illinois University at Carbondale   (United States)

Author keywords

Automatic test pattern generation (ATPG); Delay testing; Testing; Timing analysis; Verification

Indexed keywords

AUTOMATIC TESTING; BENCHMARKING; BOOLEAN FUNCTIONS; COMPUTER AIDED LOGIC DESIGN; GRAPH THEORY; OPTIMIZATION;

AUTOMATIC TEST PATTERN GENERATION (ATPG); DELAY TESTING; TIMING ANALYSIS; VERIFICATION;

COMBINATORIAL CIRCUITS;

EID: 2942541392     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2004.828112     Document Type: Article

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