-
1
-
-
0022044739
-
Cuttina chip-testing costs
-
SETH, S.C., and AGRAWAL, V.D.: Cuttina chip-testing costs, IEEE Spectrum. 1985, 4, pp. 38-45
-
IEEE Spectrum. 1985, 4, Pp. 38-45
-
-
Seth, S.C.1
Agrawal, V.D.2
-
2
-
-
0016485480
-
Polynomially complete fault . detection problems
-
IBARRA, O.H., and SAHNI, S.K.: Polynomially complete fault . detection problems, IEEE Trans., 1975, C-24, (3), pp. 242-249
-
IEEE Trans., 1975, C-24, (3), Pp. 242-249
-
-
Ibarra, O.H.1
Sahni, S.K.2
-
4
-
-
0001413253
-
Diagnosis of automata failures: A calculus and a method
-
ROTH, J.P.: Diagnosis of automata failures: A calculus and a method, IBM J. Res. Dev:, 1966, 10, (4), pp. 278-291
-
IBM J. Res. Dev:, 1966, 10, (4), Pp. 278-291
-
-
Roth, J.P.1
-
5
-
-
0019543877
-
An implicit enumeration algorithm to generate tests for combinational logic
-
GOEL, P.: An implicit enumeration algorithm to generate tests for combinational logic, IEEE Trans., 1981, C-30, (3), pp. 215-222
-
IEEE Trans., 1981, C-30, (3), Pp. 215-222
-
-
Goel, P.1
-
6
-
-
0020923381
-
On the acceleration of test generation algorithms
-
FUJIWARA, H., and SHIMONO, T.: On the acceleration of test generation algorithms, IEEE Trans., 1983, C-32, (12), pp. 1137-1144
-
IEEE Trans., 1983, C-32, (12), Pp. 1137-1144
-
-
Fujiwara, H.1
Shimono, T.2
-
7
-
-
0023865139
-
SOCRATES: A highly efficient automatic test pattern generation system
-
SCHULZ, M.H., TRISCHLER, E., and SARFERT, T.M.: SOCRATES: A highly efficient automatic test pattern generation system, IEEE Traits., 1988, CAD-7, (1), pp. 126-137
-
IEEE Traits., 1988, CAD-7, (1), Pp. 126-137
-
-
Schulz, M.H.1
Trischler, E.2
Sarfert, T.M.3
-
8
-
-
0026677403
-
Search state equivalence for redundancy identification and test generation
-
GIRALDI, J., and BUSHNELL, M.L.: Search state equivalence for redundancy identification and test generation. Proceedings of the international conference on Test, Nashville, TN, USA, 1991, pp. 184-193
-
Proceedings of the International Conference on Test, Nashville, TN, USA, 1991, Pp. 184-193
-
-
Giraldi, J.1
Bushnell, M.L.2
-
9
-
-
0039607679
-
Analyzing errors with the Boolean difference
-
SELLERS, E.F., HSIAO, M.Y., and BEARNSON, L.W.: Analyzing errors with the Boolean difference, IEEE Trans., 1968, C-17, (7), pp. 676-683
-
IEEE Trans., 1968, C-17, (7), Pp. 676-683
-
-
Sellers, E.F.1
Hsiao, M.Y.2
Bearnson, L.W.3
-
10
-
-
0026623575
-
Test pattern generation using Boolean satisfiability
-
LARRABEE, T.: Test pattern generation using Boolean satisfiability, IEEE Trans., 1992, CAD-11, (1), pp 4-15
-
IEEE Trans., 1992, CAD-11, (1), Pp 4-15
-
-
Larrabee, T.1
-
11
-
-
0027634569
-
A transitive closure algorithm for test generation
-
CHAKRADHAR, ST., AGARWAL, V.D., and ROTHWEILER, S.G.: A transitive closure algorithm for test generation, IEEE Trans., 1993, CAD-12, (7), pp. 1015-1028
-
IEEE Trans., 1993, CAD-12, (7), Pp. 1015-1028
-
-
Chakradhar, S.T.1
Agarwal, V.D.2
Rothweiler, S.G.3
-
12
-
-
0029545582
-
An efficient method for generating exhaustive test sets
-
STANION, R.T., BHATTACHARYA, D., and SECHEN, C: An efficient method for generating exhaustive test sets, IEEE Trans., 1995, CAD-14, (12), pp. 1516-1525
-
IEEE Trans., 1995, CAD-14, (12), Pp. 1516-1525
-
-
Stanion, R.T.1
Bhattacharya, D.2
Sechen, C.3
-
13
-
-
0030247603
-
Combinational test generation using satisfiability
-
STEPHAN, P., BRAYTON, R.K., and SANGIOVANNI-VINCENTELLI, A.L.: Combinational test generation using satisfiability, IEEE Trans., 1996, CAD-15, (9), pp. 1167-1176
-
IEEE Trans., 1996, CAD-15, (9), Pp. 1167-1176
-
-
Stephan, P.1
Brayton, R.K.2
Sangiovanni-Vincentelli, A.L.3
-
14
-
-
84903828974
-
Representation of switching circuits by binary-decision programs
-
LEE, C.Y.: Representation of switching circuits by binary-decision programs, Bell Sys. Tech. J., 1992, 38, (7), pp. 985-999
-
Bell Sys. Tech. J., 1992, 38, (7), Pp. 985-999
-
-
Lee, C.Y.1
-
15
-
-
0027644520
-
-
ORTEGA, J., LLORIS, A., PRIETO, A., and PELAYO, F.J.: Test-pattern generation based on Reed-Muller coefficients, IEEE Trans., 1993, C-12, (8), pp. 968-980
-
IEEE Trans., 1993, C-12, (8), Pp. 968-980
-
-
Ortega, J.1
Lloris, A.2
Prieto, A.3
Pelayo, F.J.4
-
16
-
-
0024681171
-
Fault detection in combinational networks by Reed-Muller transforms
-
DAMARLA, T.R., and KARPOVSKY, M.: Fault detection in combinational networks by Reed-Muller transforms, IEEE Trans., 1989, C-38, (6), pp. 788-797
-
IEEE Trans., 1989, C-38, (6), Pp. 788-797
-
-
Damarla, T.R.1
Karpovsky, M.2
-
18
-
-
33745981730
-
Evaluation of test generation algorithms
-
MIN, Y., and LI, Z.: Evaluation of test generation algorithms, llth symposium on VLSI test, NJ, USA, 1993, pp. 348-350
-
Llth Symposium on VLSI Test, NJ, USA, 1993, Pp. 348-350
-
-
Min, Y.1
|