A dual-mode wavelet based r-wave detector using single-vt for leakage reduction

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 1330-1333

  Rodrigues, Joachim Neves ^a   Olsson, Thomas ^a   Sörnmo, Leif ^a   Öwall, Viktor ^a  

^a LUND UNIVERSITY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

CARDIAC PACEMAKERS; CLOCK FREQUENCY; CMOS TECHNOLOGY; DUAL MODES; LEAKAGE POWER; LEAKAGE REDUCTION; NOISE DETECTION; NOISY ENVIRONMENT; PERFORMANCE DEGRADATION; POWER CONSUMPTION; POWER ESTIMATIONS; POWER SOURCES; POWER-SUPPLY RAILS; WAVE DETECTORS; ZERO CROSSING RATE;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; ELECTRIC POWER UTILIZATION; PACEMAKERS;

DETECTORS;

EID: 29344472425     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2005.1464841     Document Type: Conference Paper

References (11)

1. M. Å ström, S. Olmos, and L. Sörnmo, "Wavelet based event detection in pacemakers," in Proc. 23rd annual EMBS Intl. Conf., 2001.
2. J. N. Rodrigues, V. Ö wall, and L. Sörnmo, "A wavelet based R-wave detector for cardiac pacemakers in 0.35 CMOS technology," in Proc. of the 2004 IEEE Intl. Symp. on Circuits and Systems.
3. A. Gerosa and A. Neviani, "A very low-power 8- bitΣΔconverter in a 0.8μm CMOS technology for the sensing chain of a cardiac pacemaker, operating down to 1.8V," in Proc. 2003 IEEE Intl. Symp. Circuits Systems.
4. t low-leakage gated-ground cache for deep submicron," IEEE Journ. Solid-State Circuits, 2003.
5. J. N. Rodrigues, V. Ö wall, and L. Sörnmo, "R-wave detection for pacemakers using a matched filter based on an artificial neural network," in Proc. 2002 Intl. Conf. Neural Inf. Processing.
6. J. Deller, J. Hansen, and J. Proakis, Discrete-time Processing of Speech Signals. Wiley, 2000.
7. J. Webster, Design of cardiac pacemakers. New York, USA: IEEE Press, 1995.
8. K. Nazifi and G. Hansson, "Industry's first RTL power optimization feature significantly improves power compiler's quality of results." www.synopsys.com/news/pubs/rsvp/spr98/rsvp-spr98-6.html, 1998.
9. J. M. Rabaey, A. Chandrakasan, and B. Nikolić, Digital Integrated Cicuits. Prentice Hall, 2003.
10. Y. Ye, S. Borkar, and V. DE, "A new technique for standy leakage reduction in high-performance circuits," in Symp. on VLSI Circuits Digest of Tech. Papers 1998.
11. W. Qifa, T. Yujing, and X. Wei, "Oki techno centre design team achieves lowest power consumption using power compiler." www.synopsys.com/news/pubs/compiler/art1lead-oki-dec02.html.