On the Computational Synthesis of CMOS Voltage Followers

IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

Volumn E88-A, Issue 12, 2005, Pages 3479-3484

  Tlelo Cuautle, Esteban ^a,b,c   Torres Muñoz, Delia ^a   Torres Papaqui, Leticia ^a  

^a INSTITUTO NACIONAL DE ASTROFÍSICA   (Mexico)

^b ITPE   (Mexico)

^c IEEE   (Mexico)

Author keywords

Analog synthesis; Biasing and sizing; CAD; MOSFET; Norator; Nullator; Voltage follower

Indexed keywords

COMPUTATIONAL METHODS; COMPUTER AIDED DESIGN; ELECTRIC CURRENTS; ELECTRIC POTENTIAL; MOSFET DEVICES; SYNTHESIS (CHEMICAL);

ANALOG SYNTHESIS; BIASING AND SIZING; NORATOR; NULLATOR; VOLTAGE FOLLOWERS;

CMOS INTEGRATED CIRCUITS;

EID: 29144456034     PISSN: 09168508     EISSN: 17451337     Source Type: Journal    
DOI: 10.1093/ietfec/e88-a.12.3479     Document Type: Article

References (13)

1. C. Toumazou, B. Gilbert, and G.S. Moschytz, Trade-Offs in Analog Circuit Design, Kluwer Academic Publishers, 2002.
2. H. Schmid, "Approximating the universal active element," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol.47, no.11, pp. 1160-1169, 2000.
3. I. Miller and A. Ferreira, "Behavioral modeling in industrial IC design: Experiences and observations," IEEE BMAS Workshop, pp.37-40, 2004.
4. E. Tlelo and A. Díaz, "An heuristic circuit-generation technique for the design automation of analog circuits," IEEE Int. Symp. Circuits Syst., Proc., vol.1, pp.193-196, 2003.
5. L. Torres-Papaqui and E. Tlelo-Cuautle, "Synthesis of CCs and CFOAs by manipulation of VFs and CFs," IEEE BMAS Workshop, pp.92-96, 2004.
6. A.Ü. Keskin and A. Toker, "A NIC with impedance scaling properties using unity gain cells," Analog Integr. Circuits Signal Process., vol.41, no.1, pp.85-87, 2004.
7. S.S. Gupta and R. Senani, "New single resistance controlled oscillators employing reduced number of unity-gain cells," IEICE Electron. Express, vol.1, no.16, pp.507-512, 2004.
8. R. Senani and S.S. Gupta, "Novel sinusoidal oscillators using only unity gain voltage followers and currrent followers," IEICE Electron. Express, vol.1, no.13, pp.404-409, 2004.
9. J.M. Carrillo, R.G. Carvajal, A. Torralba, and J.F. Duque-Carrillo, "Rail-to-rail low-power high-slew-rate CMOS analogue buffer," Electron. Lett., vol.40, no.14, pp.843-844, 2004.
10. J. Ramírez-Angulo, S. Thoutam, A. Lopez-Martin, and R.J. Carvajal, "Low-voltage CMOS analog four quadrant multiplier based on flipped voltage followers," IEEE Int. Symp. Circuits Syst. Proc., vol.1, pp.681-684, 2004.
11. E. Tlelo-Cuautle, A. Quintanar-Ramos, G. Gutiérrez-Pérez, and M. González de la Rosa, "SIASCA: Interactive system for the symbolic analysis of analog circuits," IEICE Electron. Express, vol.1, no.1, pp. 19-23, 2004.
12. E. Bruun, "Class AB CMOS first generation current conveyor," Electron. Lett., vol.31, no.6, pp.422-423, 1995.
13. G. Palumbo and S. Pennisi, Feedback Amplifiers: Theory and Design, Kluwer Academic Publishers, 2002.