Raif-to-rail low-power high-slew-rate CMOS analogue buffer

Electronics Letters

Volumn 40, Issue 14, 2004, Pages 843-844

  Carrillo, J M ^a   Carvajal, R G ^b   Torralba, A ^b   Duque Carrillo, J F ^a  

^a UNIVERSITY OF EXTREMADURA   (Spain)

^b UNIVERSITY OF SEVILLE   (Spain)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; COMPUTER SIMULATION; ELECTRIC POTENTIAL; ENERGY UTILIZATION; RELIABILITY; SIGNAL TO NOISE RATIO; TRANSISTORS;

LOW-POWER HIGH-SLEW-RATE; PMOS; RAIL-TO-RAIL OPERATION; VOLTAGE LEVEL SHIFTER;

CMOS INTEGRATED CIRCUITS;

EID: 3142729132     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:20045047     Document Type: Article

References (3)

1. Van Petegem, P.M., and Duque-Carrillo, J.F.: 'Compact high-frequency output buffer for testing of analog CMOS VLSI circuits', IEEE J. Solid-State Circuits, 1989, 24, pp. 540-542
2. Elwan, H., and Ismail, M.: 'CMOS low noise class AB buffer', Electron. Lett., 1999, 35, pp. 1834-1836
3. Torralba, A., et al.: 'Compact low-power high slew rate CMOS buffer for large capacitive loads', Electron. Lett., 2002, 38, pp. 1348-1349