A dual-mode truly modular programmable fractional divider based on a 1/1.5 divider cell

IEEE Microwave and Wireless Components Letters

Volumn 15, Issue 11, 2005, Pages 754-756

  Yang, Yu Che ^a   Yu, Shih An ^a   Wang, Tao ^a   Lu, Shey Shi ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

50 duty cycle and phase locked loop (PLL); Fractional divider; Programmable divider

Indexed keywords

CELLS; CMOS INTEGRATED CIRCUITS; PHASE LOCKED LOOPS; TRIGGER CIRCUITS;

50% DUTY CYCLE AND PHASE-LOCKED LOOP (PLL); CMOS TECHNOLOGY; PROGRAMMABLE DIVIDER;

FREQUENCY DIVIDING CIRCUITS;

EID: 28744454779     PISSN: 15311309     EISSN: None     Source Type: Journal    
DOI: 10.1109/LMWC.2005.858978     Document Type: Article

References (4)

1. A. D. Riley, A. Copeland, and A. Kwasniewski, "Delta-sigma modulation in fractional-n frequency synthesis." IEEE J. Solid-State Circuits. vol. 28. no. 5. pp. 553-559, May 1993.
2. P. Kenny, A. D. Riley, M. Filiol, and A. Copeland, "Design and realization of a digital Δ-Σ modulator for fractional-n frequency synthesis." IEEE Trans. Veh. Technol., vol. 48. no. 2. pp. 510-521, Mar. 1999.
3. R. Magoon and A. Molnar, "RF local oscillator path l'or GSM direct conversion transceiver with true 50% duty cycle divide by three and active third harmonic cancellation." in Proc. IEEE RFIC Symp., Jun. 2002, pp. 20-23.
4. S. Vaucher, I. Ferencic, M. Locher, S. Sedvallson, U. Voegeli, and Z. Wang, "A family of low-power truly modular programmable dividers in standard 0.35-um CMOS technology." IEEE. J. Solid-State Circuits, vol. 35. no. 7, pp. 1039-1045, Jul. 2000.