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Volumn , Issue , 2005, Pages 565-572

Electrical characteristics and reliability of extended drain voltage NMOS devices with multi-resurf junction

Author keywords

Breakdown, reliability; Extended drain voltage MOS; Hot carrier degradation; RESURF LDMOS

Indexed keywords

BREAKDOWN, RELIABILITY; EXTENDED DRAIN VOLTAGE MOS; HOT CARRIER DEGRADATION; RESURF LDMOS;

EID: 28744453583     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (11)

References (11)
  • 1
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    • D. Monticelli, "Taking a system approach to Energy Management", p 15-19, Proc of ESSDERC, 2003
    • (2003) Proc of ESSDERC , pp. 15-19
    • Monticelli, D.1
  • 3
    • 15744381102 scopus 로고    scopus 로고
    • ESD protection of double-diffusion devices in submicron CMOS processes
    • A. Concannon, V. A. Vashchenko, M. ter Beek, and P. Hopper, "ESD Protection of Double-Diffusion Devices in Submicron CMOS Processes", in Proceed. of ESSDERC, 2004. pp.261-264
    • (2004) Proceed. of ESSDERC , pp. 261-264
    • Concannon, A.1    Vashchenko, V.A.2    Ter Beek, M.3    Hopper, P.4
  • 4
    • 0033279805 scopus 로고    scopus 로고
    • Wide range control of the sustaining voltage of ESD protection elements realized in a smart power technology
    • H. Gossner, T. Muller-Lynch, K. Esmark, M. Stecher, " Wide range control of the sustaining voltage of ESD protection elements realized in a smart power technology," Proceed of ESD/EOS Symposium, 1999, pp. 19-27.
    • (1999) Proceed of ESD/EOS Symposium , pp. 19-27
    • Gossner, H.1    Muller-Lynch, T.2    Esmark, K.3    Stecher, M.4
  • 5
    • 28744441705 scopus 로고    scopus 로고
    • Method of forming Zener diode in a NPN and PNP Bipolar process flow that requires no additional steps to set the breakdown voltage, US Patent 6,386,317, Jul/1
    • V.A. Vashchenko, A. Strachan, P. Hopper "Method of forming Zener diode in a NPN and PNP Bipolar process flow that requires no additional steps to set the breakdown voltage, US Patent 6,386,317, Jul/1, 2003.
    • (2003)
    • Vashchenko, V.A.1    Strachan, A.2    Hopper, P.3
  • 6
    • 0032256942 scopus 로고    scopus 로고
    • A new generation of high voltage MOSFETs breaks the limit line of silicon
    • G. Deboy et.al, "A new generation of high voltage MOSFETs breaks the limit line of silicon", IEDM, pp.683-685, 1998
    • (1998) IEDM , pp. 683-685
    • Deboy, G.1
  • 7
    • 0034449069 scopus 로고    scopus 로고
    • Mdmesh: Innovative technology for high voltage power MOSFETs
    • M.Saggio, D.Fagone, S. Masumeci, "Mdmesh: innovative technology for high voltage power MOSFETs," Proc. ISPSD 200, pp.65-68, 2000.
    • (2000) Proc. ISPSD , vol.200 , pp. 65-68
    • Saggio, M.1    Fagone, D.2    Masumeci, S.3
  • 8
    • 0034297791 scopus 로고    scopus 로고
    • 120V Interdigitated-Drain LDMOS (IDLDMOS) on SOI substrate breaking power LDMOS limit
    • S.Xu, et al. "120V Interdigitated-Drain LDMOS (IDLDMOS) on SOI Substrate Breaking Power LDMOS Limit," IEEE Trans on Elec. Dev., 47, N10, 2000, pp.1980-1985.
    • (2000) IEEE Trans on Elec. Dev. , vol.47 , Issue.10 , pp. 1980-1985
    • Xu, S.1
  • 9
    • 17044368807 scopus 로고    scopus 로고
    • ESD protection of the high voltage tolerant pins in low-voltage BiCMOS processes
    • V. A. Vashchenko, M. ter Beek, W. Kindt, and P. Hopper "ESD protection of the high voltage tolerant pins in low-voltage BiCMOS processes", in Proceed of BCTM, 2004. pp. 277-280.
    • (2004) Proceed of BCTM , pp. 277-280
    • Vashchenko, V.A.1    Ter Beek, M.2    Kindt, W.3    Hopper, P.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.