Metastability tests of flip-flops in programmable digital circuits

Microelectronics Journal

Volumn 37, Issue 2, 2006, Pages 174-180

  Kalisz, J ^a   Jachna, Z ^a  

^a MILITARY UNIVERSITY OF TECHNOLOGY   (Poland)

Author keywords

Flip flop; Mean time between failures; Metastability; Metastability test; Programmable digital circuits

Indexed keywords

CMOS INTEGRATED CIRCUITS; DETECTORS; DIGITAL CIRCUITS; MATHEMATICAL MODELS;

MEAN TIME BETWEEN FAILURES; METASTABILITY; METASTABILITY TEST;

FLIP FLOP CIRCUITS;

EID: 28644447596     PISSN: 00262692     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.mejo.2005.04.042     Document Type: Article

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