Application of CPL mask for whole chip 65nm DRAM patterning

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 5853 PART II, Issue , 2005, Pages 835-843

  Lin, Orson ^a   Hung, Richard ^b   Lee, Booky ^a   Wu, Yuan Hsun ^b   Kozuma, Makoto ^a   Shih, Chiang Lin ^b   Lin, Jengping ^b   Hsu, Michael ^c   Hsu, Stephen D ^c  

^a Toppan Chunghwa Electronics Co Ltd   (Taiwan)

^b NANYA TECHNOLOGY CORPORATION   (Taiwan)

^c ASML US Inc   (United States)

Author keywords

CD Uniformity; Chromeless Phase Lithography (CPL); CPL; E beam 2nd writing; MEEF; Optical Proximity Correction (OPC); Process Window (PW); RET

Indexed keywords

ETCHING; OPTICAL RESOLVING POWER; WSI CIRCUITS;

CPL; MEEF; RET;

MICROPROCESSOR CHIPS;

EID: 28544437391     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.617230     Document Type: Conference Paper

References (4)

1. nd writing in mask alignment accuracy and pattern faultless for CPL technology" SPIE Vol. 5645
2. Chun-hung Lin et. al., "Investigation of Phase Variation Impact on CPL PSM for Low K1 Imaging" SPIE Vol. 5130
3. Stephen D. Hsu et. al., "Low K1 Lithography Patterning Options for the 90nm and 65nm Nodes" SPIE Vol. 5130
4. Allen Wu et. Al, "Manufacturing Implementation of 65nm DRAM Using ArF Exposure with CPL Mask" SPIE Vol. 5754