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Proceedings - IEEE International Symposium on Circuits and Systems

Volumn , Issue , 2005, Pages 6138-6141

A 4-Bit 5GS/s flash A/D converter in 0.18μm CMOS

(3) Sheikhaei, Samad a Mirabbasi, Shahriar a Ivanov, Andre a

a UNIVERSITY OF BRITISH COLUMBIA (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

A/D CONVERTER; CMOS TECHNOLOGY; DIGITAL CIRCUITRY; DNL ERROR; FLASH ANALOG-TO-DIGITAL CONVERTERS; FLASH-ADC; HIGH-SPEED; LOW SWING; LOW-POWER OPERATION; OFFSET AVERAGING; OFFSET VOLTAGE; SIMULATION RESULT; STANDARD DEVIATION; TIME-INTERLEAVED;

CMOS INTEGRATED CIRCUITS;

MULTICARRIER MODULATION;

EID: 28444474300 PISSN: 02714310 EISSN: None Source Type: Conference Proceeding
DOI: 10.1109/ISCAS.2005.1466041 Document Type: Conference Paper

Times cited : (32)

References (8)

1
- 0033281382
- GAD: A 12GS/s CMOS 4-bit A/D converter for an equalized multilevel link
- June
- W. Ellersick, C. K. Yang, M. Horowitz, and W. Dally; "GAD: A 12GS/s CMOS 4-bit A/D converter for an equalized multilevel link," IEEE Symp. VLSI Circuits, Dig.Tech. Papers, June 1999, pp. 49-52.
- (1999) IEEE Symp. VLSI Circuits, Dig.Tech. Papers , pp. 49-52
- Ellersick, W.¹ Yang, C.K.² Horowitz, M.³ Dally, W.⁴

2
- 0035505542
- A serial-link transceiver based on 8-G samples/s A/D and D/A converters in 0.25μm CMOS
- Nov
- C. K. Yang, V. Stojanovic, S. Mojtahedi, M. Horowitz, W. Ellersick, "A serial-link transceiver based on 8-G samples/s A/D and D/A converters in 0.25μm CMOS," IEEE J. Solid-State Circuits, vol. 36, pp. 293-301, Nov. 2001.
- (2001) IEEE J. Solid-State Circuits , vol.36 , pp. 293-301
- Yang, C.K.¹ Stojanovic, V.² Mojtahedi, S.³ Horowitz, M.⁴ Ellersick, W.⁵

3
- 0346342442
- Nathawad, Urata, Wooley and Miller, A 40-GHz-bandwidth, 4-bit, time-interleaved A/D converter using photoconductive sampling, IEEE J. Solid-State Circuits, 38, pp 2021 - 2030, Dec. 2003.
- Nathawad, Urata, Wooley and Miller, "A 40-GHz-bandwidth, 4-bit, time-interleaved A/D converter using photoconductive sampling", IEEE J. Solid-State Circuits, vol. 38, pp 2021 - 2030, Dec. 2003.

4
- 60649093967
- A 4-bit analog-to-digital converter for high-speed serial links
- Quebec, Canada, pp
- S. Naraghi and D. Johns, "A 4-bit analog-to-digital converter for high-speed serial links", Micronet Annual Workshop, April 26-27, 2004, Aylmer, Quebec, Canada, pp. 33-34.
- Micronet Annual Workshop, April 26-27, 2004, Aylmer , pp. 33-34
- Naraghi, S.¹ Johns, D.²

5
- 0035696160
- A 6b 1.3Gsample/s A/D converter in 0.35μm CMOS
- Dec
- Choi, Abidi, "A 6b 1.3Gsample/s A/D converter in 0.35μm CMOS", IEEE J. Solid-State Circuits, vol. 36, pp. 1847 -1858, Dec. 2001.
- (2001) IEEE J. Solid-State Circuits , vol.36 , pp. 1847-1858
- Choi, A.¹

6
- 0036917305
- A 6-b 1.6-Gsample/s flash ADC in 0.18μm CMOS using averaging termination
- Dec
- P. Scholtens and M. Vertregt, "A 6-b 1.6-Gsample/s flash ADC in 0.18μm CMOS using averaging termination," IEEE J. Solid-State Circuits, Vol. 37, pp. 1599 -1609, Dec. 2002.
- (2002) IEEE J. Solid-State Circuits , vol.37 , pp. 1599-1609
- Scholtens, P.¹ Vertregt, M.²

7
- 0030655867
- Design of sample-and-hold amplifiers for high-speed low-voltage A/D converters
- May
- B. Razavi, "Design of sample-and-hold amplifiers for high-speed low-voltage A/D converters," Custom Integrated Circuits Conf., May 1997, pp. 59-66.
- (1997) Custom Integrated Circuits Conf , pp. 59-66
- Razavi, B.¹

8
- 0036544662
- Speed-power-accuracy tradeoff in high-speed CMOS ADCs
- April
- K. Uyttenhove and M. Steyaert, "Speed-power-accuracy tradeoff in high-speed CMOS ADCs" IEEE Trans. Circuits and Systems II: Analog and Digital Signal Processing, Vol. 49, pp. 280-287, April 2002.
- (2002) IEEE Trans. Circuits and Systems II: Analog and Digital Signal Processing , vol.49 , pp. 280-287
- Uyttenhove, K.¹ Steyaert, M.²

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.