Parametric built-in self-test of VLSI systems

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 1999, Pages 376-380

  Niggemeyer, D ^a   Ruffer, M ^a,b  

^a LEIBNIZ UNIVERSITY HANNOVER   (Germany)

^b SIEMENS AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ACCURACY PROBLEMS; AUTOMATIC TEST EQUIPMENT; CIRCUIT UNDER TEST; DESIGN CONSTRAINTS; MAXIMUM FREQUENCY; OVERALL TIMING ACCURACIES; PARAMETRIC TEST; PHASELOCKED LOOP (PLLS);

AUTOMATIC TESTING; BUILT-IN SELF TEST; CMOS INTEGRATED CIRCUITS; DESIGN; EQUIPMENT TESTING; EXHIBITIONS; PHASE LOCKED LOOPS;

INTEGRATED CIRCUIT TESTING;

EID: 0142046638     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.1999.761149     Document Type: Conference Paper

References (11)

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