An ECG signal acquisition system integrated in a 0.35 μm CMOS technology

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 5839, Issue , 2005, Pages 228-237

  Zhou, Lingchuan ^a   Bozier, Anthony ^a   Blonde, Jean Philippe ^a   Kraemer, Michel ^b   Felblinger, Jacques ^c   Braun, Francis ^a  

^a CNRS   (France)

^b ZAE Sud Intercommunale   (France)

^c UNIVERSITÉ DE LORRAINE   (France)

Author keywords

CMOS; ECG; Gm c filter; Low consumption; Offset compensation

Indexed keywords

AMPLIFIERS (ELECTRONIC); ANALOG TO DIGITAL CONVERSION; CMOS INTEGRATED CIRCUITS; SIGNAL PROCESSING;

GM-C FILTER; GM-C STRUCTURE; LOW CONSUMPTION; OFFSET COMPENSATION;

ELECTROCARDIOGRAPHY;

EID: 28344435601     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1117/12.608674     Document Type: Conference Paper

References (14)

1. D.Rowlands, D.A.James, C.Vanegas, S.RAO, P.Lisner, "Design and fabrication of an ECG amplifier on silicon using standard CMOS process", Sensors, 2003, Proceedings of IEEE, Volume 2, 22-24, Vol.2, Pages: 1348-1352, 2003.
2. R.Martins, S.Selberherr, F.Vaz, "A CMOS IC for portable EEG acquisition systems, Instrumentation and Measurement Technology Conference", IEEE Transactions on Instrumentation and measurement, Vol. 47, Issue 5, Pages: 1191-1196, 1998.
3. T.Desel, T.Reichel, S.Rudischhauser, H.Hauer, "A CMOS nine channel ECG measurement", ICASIC, 1996, 2nd International Conference, Pages: 115-118, 1996.
4. G.Mc Glinchey, S.Pietkiewicz, R.Frank, P.Schmidt-Andersen, F.Hansen, "A programmable medical data acquisition system chip", Custom Integrated Circuits Conference, 1988, Proceedings of the IEEE 1988, 16-19 May 1988, Pages: 9.4/1-9.4/6, 1998.
5. J. Nurmi, M. Williams, P. Jarvilehto, E.K.-P.stola, A.Ruha, T.Karema, H.Tenhunen, "An integrated sensor interface circuit for ECG measurements", CompEuro '89., 'VLSI and Computer Peripherals, VLSI and Microelectronic Applications in Intelligent Peripherals and their Interconnection Networks, Proceedings, 8-12 May 1989, Pages: 3/164-3/166, 1989.
6. K-J.LEE, W-C.WANG, "A 0.5μm concurrent testable chip of a fifth-order Gm-C filter", Analog Integrated Circuits and Signal Proceedings, 32, Pages: 231-247, 2002.
7. V.I.Prodanov, M.M.Green, "Improved Biquad Structures Using Double-Output Transconductance Blocks for Tunable Continuous-Time Filters", Analog Integrated Circuits and Signal Proceedings, 13, Pages: 233-240, 1997.
8. B.Linares-Barranco and al. "Current mode techniques for sub-pico-ampere circuit design", Analog Integrated Circuits and Signal Proceedings, 38, Pages: 103-119, 2004.
9. C-G.Yu, L.G.Randle, "An automatic offset compensation scheme with ping-pong control for CMOS operational amplifiers", IEEE Journal of solid-state circuits, Vol. 29, Issue 5, Pages: 601-610, 1994.
10. C.C Enz, G.C.Temes, "Circuit techniques for reducing the effects of op-amp imperfections: autozeroing, correlated double sampling, and chopper stabilization", Proceedings of the IEEE, Vol. 84, Issue 11, Nov. 1996, Pages: 1584-1614, 1996.
11. C.Menolfi, Q.Huang, "A fully integrated, untrimmed CMOS instrumentation amplifier with submicrovolt offset", Solid-State Circuits, IEEE Journal of Vol. 34, Issue 3, March 1999, Pages: 415-420, 1999.
12. A.Bakker, K.Thiele, J.H.Huijsing, "A CMOS nested-chopper instrumentation amplifier with 100-nV offset", Solid-State Circuits, IEEE Journal of Volume 35, Issue 12, Dec. 2000, Pages: 1877-1883, 2000.
13. M.Kayal, R.T.L.Saez, M.Declercq, "An automatic offset compensation technique applicable to existing operational amplifier core cell", Custom Integrated Circuits Conference, Proceedings of the IEEE 1998, 11-14 May 1998, Pages: 419-422, 1998.
14. C.-S.Wang; P-C.Huang, "A CMOS low-IF programmable gain amplifier with speed-enhanced DC offset cancellation", ASIC, 2002. Proceedings, 2002 IEEE Asia-Pacific Conference on 6-8 Aug. 2002, Pages: 133-136, 2002.