A 0.5 μm concurrent testable chip of a fifth-order gm-C filter

Analog Integrated Circuits and Signal Processing

Volumn 32, Issue 3, 2002, Pages 231-247

  Lee, Kuen Jong ^a   Wang, Wei Chiang ^a  

^a NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

Author keywords

Concurrent testing; gm C filter; Testable design

Indexed keywords

CMOS INTEGRATED CIRCUITS; DESIGN FOR TESTABILITY; DIGITAL INTEGRATED CIRCUITS; ERROR DETECTION; LOW PASS FILTERS;

CONCURRENT TESTING; CURRENT MODE METHOD;

INTEGRATED CIRCUIT TESTING;

EID: 0036754881     PISSN: 09251030     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1020347608924     Document Type: Article

References (15)

1. Abramovici, M., Breuer, M. A. and Friedman, A. D., Digital Systems Testing and Testable Design. W. H. Freeman and Company, 1990.
2. Lidgey, F. J., Toumazou, C. and Haigh, D. G., Analogue IC Design: The Current-Mode Approach. Peter Peregrinus on beha, London, U.K., 1990.
3. Kardontchik, J. E., Introduction to the Design of Transconductor-Capacitor Filters. Kluwer Academic Publishers, 1992.
4. Wey, C. L., "Built-in self-test (BIST) structure for analog circuit fault diagnosis." IEEE Tran. on Instrumentations and Measurement 39(3), pp. 517-521, June 1990.
5. Vázquez, D., Rueda, A. and Huertas, J. L., "A new strategy for testing analog filters." IEEE VLSI Test Symp., pp. 36-41, 1994.
6. Huang, K. H. and Abraham, J. A., "Algorithm-based fault tolerance for matrix operations." IEEE Tran. on Computers C-33(6), pp. 518-528, June 1984.
7. Jou, J. Y. and Abraham, J. A., "Fault-tolerant matrix arithmetic and signal processing on highly concurrent computing structures," in Proceedings of IEEE 74(5), pp. 732-741, May 1986.
8. Chatterjee, A., "Concurrent error detection in linear analog and switched-capacitor state variable systems using continuous checksums," in Proc. Int'l. Test Conf., pp. 582-591, 1991.
9. Chatterjee, A., "A new approach to fault-tolerance in linear analog systems based on checksum-coded state space representations," in Proc. Int'l. Conf. on Computer Design, pp. 478-481, 1992.
10. Chatterjee, A., "Concurrent error detection and fault-tolerance in linear analog circuits using continuous checksums." IEEE Trans. on Very Large Scale Integration (VLSI) Systems 1(2), pp. 138-150, June 1993.
11. Jeong, MoonJae, Takagi, S., Czarnul, S. and Fujii, N., "Design of a novel linear 3-input CMOS OTA and its application to filter realization," in Proceedings of IEEE Asia Pacific Conference on Circuits and Systems '96, pp. 121-124, November 1996.
12. Szczepánski, S., Wyszyński, A. and Schaumann, R., "Highly linear voltage-controlled CMOS transconductors." IEEE Trans. on Circuits and Systems-I: Fundamental Theory and Applications 40(4), pp. 258-262, April 1993.
13. Gregorian, R. and Temes, G. C., "Analog MOS Integrated Circuits for Signal Processing." John Wiley and Sons Inc., New York, 1986.
14. Schaumann, R., Ghausi, M. S. and Laker, K. R., Design of Analog Filters: Passive, Active RC, and Switched Capacitor. Prentice-Hall, 1990.
15. Wang, ZhenHua, "Current-mode CMOS integrated circuits for analog computation and signal processing: A Tutorial." Analog Integrated Circuits and Signal Processing 1, pp. 287-295, 1991.