Models for interconnect capacitance extraction

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn 2001-January, Issue , 2001, Pages 167-172

  Husain, Asim ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; EXTRACTION; INTEGRATED CIRCUIT INTERCONNECTS; NUMERICAL METHODS;

ANALYTIC MODELS; CAPACITANCE EXTRACTION; CAPACITANCE MODEL; FRINGING FIELDS; INTERCONNECT CAPACITANCE; LARGE STRUCTURES; RANDOM-WALK METHOD; VLSI TECHNOLOGY;

STRUCTURAL DESIGN;

EID: 84949965579     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2001.915222     Document Type: Conference Paper

References (6)

1. N.D. Arora, K.V. Raol, R. Schumann and L.M. Richardson "Modeling and Extraction of Interconnect Capacitances for Multilayer VLSI Circuits" IEEE tran. on CAD of Integrated Circuits, Vol 15, no. 1, Jan. 1996.
2. Y.L. Le Coz, H.J. Greub and R.B. Iverson "Performance of Random Walk Capacitance Extractors for IC Interconnects: A Numerical Study" Sematch Report, March 1995.
3. B. Krauter, Y. Xia, A. Dengi and L.T. Pillegi "A Sparse Image Method of BEM Capacitance Extraction" Research Report No. CMUCAD-96-13, March 1996.
4. K. Nabours, S. Kim and J. White "Fast capacitance extraction of general three dimensional structures" IEEE tran. on Microwave theory and Techniques, 40(7): 1496-1506, July 1992.
5. Y.L. Le Coz, and R.B. Iverson, "A Stochastic Algorithm for High Speed Capacitance Extraction in Integrated Circuits", Solid State Electronics 35, pp. 1005-1012, 1991.
6. K.J. Chang, N.H. Chang, S.Y. Oh and K. Lee "Parameterized SPICE subcircuits for multilevel Interconnect modeling and Simulations", IEEE tran. on Circuits and Systems, Vol 39, No 11, Nov. 1992.