The impact of inductance on transients affecting Gate Oxide Reliability

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2005, Pages 709-713

  Nagaraj, N S ^a   Hunter, William R ^a   Balsara, Poras ^b   Cantrell, Cyrus ^b  

^a TEXAS INSTRUMENTS   (United States)

^b UNIVERSITY OF TEXAS AT DALLAS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE MATRIX; GATE OXIDE RELIABILITY (GOR); SELF-INDUCTANCE;

APPROXIMATION THEORY; CAPACITANCE; INDUCTANCE; MATHEMATICAL MODELS;

INTEGRATED CIRCUIT LAYOUT;

EID: 27944500253     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICVD.2005.164     Document Type: Conference Paper

References (6)

1. A. E. Ruehli, "Inductance Calculations in a Complex Integrated Circuit Environment," IBM J. Res. Develop., pp. 470-481, Sept. 1972.
2. M. Beattie, L. Pileggi, "Inductance 101: Modeling and Extraction," in Proceedings of DAC 2001.
3. P. E. Nicollian, W. R. Hunter, and J. C. Hu, "Experimental Evidence for Voltage Driven Breakdown Models in Ultrathin Gate Oxides," in IEEE Proc. Int. Reliability Phys. Symp (IRPS), April 2000, pp. 7-15.
4. W. R. Hunter, "The Analysis of Oxide Reliability Data," in IEEE Final Report Intl. Integrated Reliability Workshop (IRW), October 1998, pp. 114-134.
5. ox Variations, With Applications to Process Design, Circuit Design, and End Use," in IEEE Proc. Int. Reliability Phys. Symp (IRPS), March 1999, pp. 72-81.
6. A. Berman, "Time-zero dielectric reliability test by a ramp method," in IEEE Proc. Int. Reliability Phys. Symp (IRPS), 1981, pp. 204-209.