Copper-filled through wafer vias with very low inductance

Proceedings of the IEEE 2005 International Interconnect Technology Conference, IITC

Volumn , Issue , 2005, Pages 144-146

  Jenkins, Keith A ^a   Patel, Chirag S ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LOW INDUCTANCE; NETWORK ANALYZER;

APPROXIMATION THEORY; COPPER; INDUCTANCE;

SILICON WAFERS;

EID: 28244444528     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. J. Leib and M. Topper, "New Wafer-Level-Packaging Technology using Silicon-Via-Contacts For Optical And Other Sensor Applications," 2004 Electronic Components and Technology Conference, pp. 843-847 (2004 (2004).
2. L.L.W. Leung and K.J. Chen "Microwave Characterization of High Aspect Ratio Through-Wafer Interconnec Vias in Silicon Substrates, Digest of the IEEE MTT-S International Microwave Symposium, pp. 1197-1200
3. J.Wu, J. Scholvin, and J. delAlamo,"A Through-Wafer Interconnect in Silicon for RFICs", IEEE Transactions on Electron Devices, 51, pp. 1765-1771 (2004).
4. Patel, C.S., et al, "Silicon carrier with deep thru vias, fine pitch wiring and through cavity for parallel optical transceiver", 55th ECTC, Orlando, 2004.
5. J.H. Wu, J.A. del Alamo, and K.A. Jenkins, "A High Aspect-Ratio Silicon Substrate-Via Technology and Applications: Through-Wafer Interconnects for Power and Ground and Faraday Cages for SOC Isolation," Digest of the International Electron Devices Meeting, 2000, pp. 477-480.
6. M.E. Goldfarb and R.A. Pucel, "Modeling via hole grounds in microstrip," IEEE Microwave and Guided Wave Letters, 1, pp. 135-137 (1991).