A 12.5Gb/s CMOS BER test using a jitter-tolerant parallel CDR

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 47, Issue , 2004, Pages

  Ohtomo, Yusuke ^a   Kawamura, Tomoaki ^a   Nishimura, Kazuyoshi ^a   Nogawa, Masafumi ^a   Koizumi, Hiroshi ^a   Togashi, Minoru ^a  

^a NTT CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

FACTOR PLUGGABLE MODULE; JITTER TOLERANCE; PARALLEL CDR;

BANDWIDTH; BIT ERROR RATE; CAPACITANCE; DATA COMMUNICATION SYSTEMS; DETECTOR CIRCUITS; FITS AND TOLERANCES; HIGH FREQUENCY AMPLIFIERS; JITTER; LSI CIRCUITS; SIGNAL ENCODING; SWITCHING CIRCUITS; TELECOMMUNICATION; TRANSISTORS;

CMOS INTEGRATED CIRCUITS;

EID: 2442697579     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. C. Hogge. "A Self-Correcting Clock Recovery Circuit," J. Lightwave Technology, vol. LT-3, pp. 1312-1314, Dec. 1985.
2. J. Savoj, B. Razavi, " A10-Gb/s CMOS Clock and Data Recovery Circuit with a Half-Rate Linear Phase Detector," IEEE J. Solid-State Circuits, vol. 36, pp. 761-768, May 2001.
3. J. Lee, B. Razavi, "A 40-Gb/s Clock and Data Recovery Circuit in 0.18μm CMOS Technology," ISSCC Dig. Tech. Papers, pp. 242-245, Feb 2003.