A loop-bandwidth calibration system for fractional-N synthesizer and Δ∑ PLL transmitter

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages

  Akamine, Yukinori ^a   Kawabe, Manabu ^a   Hori, Kazuyuki ^a   Okazaki, Takao ^a   Tolson, Nigel ^c   Kasahara, Masumi ^b   Tanaka, Satoshi ^a  

^a HITACHI LTD   (Japan)

^b RENESAS TECHNOLOGY CORP   (Japan)

^c Renesas Technology   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 28144432342     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. Emad Hegazi and Asad A. Abidi, "A 17-mW Transmitter and Frequency Synthesizer for 900-MHz GSM Fully Integrated in 0.35-μm CMOS," IEEE J. Solid-State Circuits, vol 38, no. 5, pp.782-792, May, 2003.
2. Mikael Guenais et al., "A 18-mW Triple 2-GHz CMOS PLL for 3G Mobile System with -113 dBc/Hz GSM in-band Phase Noise and Dual-Port GMSK Modulation," IEEE MTT-S Dig., pp.185-188, June, 2003.
3. 3GPP Technical Specification 05.05 V8.9.0, "Radio Transmission and Reception," 3GPP Organizational Partners, 2001-04.