A 18 mW triple 2 GHz CMOS PLL for 3G mobile systems with - 113 dBc/Hz GSM in-band phase noise and dual-port GMSK modulation

IEEE Radio Frequency Integrated Circuits Symposium, RFIC, Digest of Technical Papers

Volumn , Issue , 2003, Pages 185-189

  Guenais, Mikaël ^a   Colomines, Stéphane ^a   Beaulaton, Hugues ^a   Gorisse, Philippe ^a  

^a MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CMOS INTEGRATED CIRCUITS; MOBILE TELECOMMUNICATION SYSTEMS; MODULATION; SPURIOUS SIGNAL NOISE;

PHASE NOISE;

PHASE LOCKED LOOPS;

EID: 0043092057     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. 3GPP specifications TSG/GERAN/WG1 05.05 "Radio Aspects"
2. J. Craninckx and M. Steyaert, « A Fully Integrated CMOS DCS-1800 Frequency Synthesizer, Proceedings of the ISSCC, 1998.
3. Woogeun Rhee, Akbar Ali, Bang-Sup Song, "A 1.1 GHz CMOS Fractional-N Frequency Synthesizer with a 3b 3rd-Order ΣΔ Modulator", Proceedings of the ISSCC, 2000.
4. Rami Ahola and Kari Halonen, "A 2GHz ΣΔ □Fractional-N Frequency Synthesizer in 0.35μm CMOS", Proceedings of the ESSCIRC, 2000.
5. Sang Oh Lee, "A 17mW, 2.5GHz Fractional-N Frequency Synthesizer for CDMA-2000", Proceedings of the ESSCIRC, 2001.
6. Alexander W. Hietala, David M. Gonzalez, Patent US 6,327,319B1 "Phase Detector with Frequency Steering".