Integrating the verification of timing, performance and correctness properties of concurrent systems

Proceedings - International Conference on Application of Concurrency to System Design, ACSD

Volumn 1998-March, Issue , 1998, Pages 109-119

  Cerone, A ^a   Kearney, D A ^a   Milne, G J ^a  

^a UNIVERSITY OF SOUTH AUSTRALIA   (Australia)

Author keywords

[No Author keywords available]

Indexed keywords

SYSTEMS ANALYSIS;

ASYNCHRONOUS HARDWARE; CONCURRENT SYSTEMS; CORRECTNESS PROPERTIES; INTEGRATED MODELLING; METHODS OF VERIFICATIONS; MICROPIPELINE; PROCESS ALGEBRAS; TIMING PROPERTIES;

TIMING CIRCUITS;

EID: 28044453888     PISSN: 15504808     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CSD.1998.657544     Document Type: Conference Paper

References (22)

1. F. Bacelli et al. Synchronisation and Linearity | Algebra for Discrete Event Systems, Wiley, 1992.
2. A. Bailey, G. A. McCaskill and G. J. Milne, \An Exercise in the Automatic Verification of Asyn- chronous Designs", Formal Methods in System Design, Vol. 4, No. 3, pp. 213-242, 1994.
3. G. Birtwistle and A. Davis (Eds), Asynchronous Digital Circuit Design, Springer, 1995.
4. T. Bolognesi, and E. Brinksma, \Introduction to the ISO specification language LOTOS", Com- puter Networks and ISDN Systems, Vol. 14, No. 1, pp. 25-59, 1987.
5. A. Cerone, A. J. Cowie, G. J. Milne, and P. A. Moseley, \Description and Verification of a Time-Sensitive Protocol", Technical Report CIS- 96-009, University of South Australia, School of Computer and Information Science, Adelaide, Australia, 1996. URL: Http://www.cis.unisa.edu.au/cgi-bin/techreport?CIS-96-009
6. A. Cerone, A. J. Cowie, G. J. Milne, and P. A. Moseley, \Modelling a Time-Dependent Protocol using the Circal Process Algebra", Lec- ture Notes in Computer Science, Vol. 1201, pp. 124-138, Springer, 1997.
7. A. Cerone, D. A. Kearney and G. J. Milne, \Verifying Bounded Delay Asynchronous Circuits using Time Relationship Constraints", Techni- cal Report CIS-97-012, University of South Aus- tralia, School of Computer and Information Sci- ence, Adelaide, Australia, 1997. URL: Http://www.cis.unisa.edu.au/cgi-bin/techreport?CIS-97-012
8. A. Cerone, D. A. Kearney and G. J. Milne, \Ver- ification of Timing, Performance and Correctness Properties of a Four-Phase Asynchrounous Mi- cropipeline", Technical Report CIS-98-002, Uni- versity of South Australia, School of Computer and Information Science, Adelaide, Australia, 1998. URL: Http://www.cis.unisa.edu.au/cgi-bin/techreport?CIS-98-002
9. A. Cerone and G. J. Milne, \Specification of Timing Constraints within the Circal Process Algebra", Lecture Notes in Computer Science, Vol. 1349, pp. 108-122, Springer, 1997.
10. T. A. Chu, C. K. C. Leung and T. S. Wanuga, \A Design Methodology for Concurrent VLSI Sys- tems", Proc. of ICDD, pp. 407-410, 1985.
11. D. l.. Dill, Trace Theory for Automatic Verifica- tion of Speed Independent Circuits, MIT Press, 1989.
12. S. Donatelli, J. Hillston and M. Ribaudo, \Com- parison of Performance Evaluation Process Alge- bra and Generalized Stochastic Petri Nets", Proc. of the 6th Int. Work. on Petri Nets and Perfor- mance Models, IEEE Comp. Soc. Press, 1995.
13. S. B.. Furber and P. Day, \Four-Phase Mi- cropipeline Latch Control Circuit", IEEE Trans- actions on Very Large Scale Integration (VLSI) Systems, Vol. 4, No. 2, pp. 247-253, 1996.
14. S. B. Furber and J. Lin, \Dynamic Logic in Four-Phase Micropipelines", Proc. of the 2nd Int. Symp. on Adv. Research in Asynchronous Cir- cuits and Systems, IEEE Comp. Soc. Press, 1996.
15. C. A. R. Hoare, Communication Sequential Pro- cesses, International Series in Computer Science, Prentice Hall, 1985.
16. G. J. Milne, \The Formal Description and Verifi- cation of Hardware Timing", IEEE Transactions on Computers, Vol. 40, No. 7, pp. 811-826, 1991.
17. G. J. Milne, Formal Specification and Verification of Digital Systems, McGraw-Hill, 1994.
18. R. Milner, Communication and Concurrency, In- ternational Series in Computer Science, Prentice Hall, 1989.
19. F. Moller. \The Semantics of Circal", Techni- cal Report HDV-3-89, University of Strathclyde, Department of Computer Science, Glasgow, UK, 1989.
20. I. E. Sutherland", \Micropipelines, Com. of ACM, Vol. 32, No. 6, pp. 720-738, 1989.
21. C. A. Vissers, G. Scollo, M. van Sinderen and E. Brinksma, \Specification Styles in Distributed Systems Design and Verification", Theoretical Computer Science, Vol. 89, pp. 179-206, 1991.
22. T. Williams, \Analyzyng and Improving the la- tency and throughput performance on self-timed pipelines and rings", Proc. of the IEEE Int. Symp. on Circuit and Systems, New York, IEEE Comp. Soc. Press, 1992.