FPGA implementation of self organizing map with digital phase locked loops

Neural Networks

Volumn 18, Issue 5-6, 2005, Pages 514-522

  Hikawa, Hiroomi ^a  

^a OITA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER HARDWARE; PHASE LOCKED LOOPS; VECTORS; WAVEFORM ANALYSIS;

DIGITAL PHASE-LOCKED LOOPS (DPLL); SOM HARDWARE; VECTOR ELEMENTS;

FIELD PROGRAMMABLE GATE ARRAYS;

ARTIFICIAL NEURAL NETWORK; COMPUTER; COMPUTER PROGRAM; CONFERENCE PAPER; INFORMATION PROCESSING; INTEGRATED CIRCUIT; PRIORITY JOURNAL; SELF ORGANIZING MAP; ALGORITHM; ARTICLE; ARTIFICIAL INTELLIGENCE;

ALGORITHMS; ARTIFICIAL INTELLIGENCE; COMPUTERS; NEURAL NETWORKS (COMPUTER);

EID: 27744448825     PISSN: 08936080     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.neunet.2005.06.012     Document Type: Conference Paper

References (10)

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