Future processors: Flexible and modular

CODES+ISSS 2005 - International Conference on Hardware/Software Codesign and System Synthesis

Volumn , Issue , 2005, Pages 4-6

  Johnson, Charlie ^a   Welser, Jeff ^a  

^a IBM   (United States)

Author keywords

Accelerators; Multiprocessor; SoC

Indexed keywords

ACCELERATORS; MULTIPROCESSORS; PROCESSOR CHIPS; SOC;

COST EFFECTIVENESS; PERFORMANCE; THROUGHPUT;

MICROPROCESSOR CHIPS;

EID: 27644595204     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. SIA, et al. International Technology Roadmap for Semiconductors, 2004 update. http://www.itrs.net/Common/2004Update/2004Update.htm
2. Ekman, M., et al. An In-Depth Look at Computer Performance Growth. Technical Report 2004-9, Chalmers University of Technology, Göteborg, Sweden, 2004.
3. Lee, B. and Brooks, D. Effects of Pipeline Complexity on SMT/CMP Power-Performance Efficiency, In Proceedings of the Workshop on Complexity-Effective Design. (WCED '05) (Madison, Wl, USA, June 5, 2005). p. 4-12. http://www.csl.cornell.edu/~alboncsi/wced05/wced05.pdf
4. th International Symposium on Computer Architecture. (ISCA '02) (Anchorage, AK, USA, May 25-29, 2002). IEEE Press, 2002, p. 14-24.
5. Gara, A. et al. Overview of the BlueGene/L system architecture. IBM Journal of Res. &Dev., 49, 2/3 (Mar./May 2005), p. 195-212.
6. Pham, D. et al. The Design and Implementation of a First-Generation CELL Processor. In ISSCC Digest of Technical Papers. (San Francisco, CA, USA, Fob 6-10, 2005) p. 184-5.