A Compact Gate-Level Energy and Delay Model of Dynamic CMOS Gates

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 52, Issue 10, 2005, Pages 685-689

  Rosselló, José L ^a   de Benito, Carol ^a   Segura, Jaume ^a  

^a UNIVERSITAT DE LES ILLES BALEARS   (Spain)

Author keywords

Circuit modeling; circuit optimization; delay estimation; power estimation

Indexed keywords

CAPACITANCE; ELECTRIC DISCHARGES; ELECTRIC SWITCHES; GATES (TRANSISTOR); MATHEMATICAL MODELS; MOSFET DEVICES; OPTIMIZATION; THRESHOLD VOLTAGE;

CIRCUIT MODELING; CIRCUIT OPTIMIZATION; DELAY ESTIMATION; POWER ESTIMATION;

CMOS INTEGRATED CIRCUITS;

EID: 27644489515     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2005.851992     Document Type: Article

References (8)

1. P. E. Gronowski et al., “High-performance microprocessor design,” IEEE J. Solid-State Circuits, vol. 33, no. 5, pp. 676–686, May 1998.
2. R. Zimmerman and W. Fichtner, “Low-power logic styles: CMOS versus pass-transistor logic,” IEEE J. Solid-State Circuits, vol. 32, no. 7, pp. 1079–1090, Jul. 1997.
3. V. De and S. Borkar, “Technology and design challenges for low power and high performance,” in Proc. ISLPED'99, pp. 163–168.
4. J. L. Rossello and J. Segura, “Charge-based analytical model for the evaluation of power consumption in sub-micron CMOS buffers,” IEEE Trans. Comput.-Aided Des. Integr. Circuits, vol. 21, no. 4, pp. 433–448, Apr. 2002.
5. J. L. Rossello and J. Segura, “Power-delay modeling of dynamic CMOS gates for circuit optimization,” in Proc. ICCAD'01, pp. 494–499.
6. T. Sakurai and R. Newton, “A simple MOSFET model for circuit analysis,” IEEE Trans. Electron Devices, vol. 38, no. 3, pp. 887–894, Apr. 1991.
7. J. L. Rossello and J. Segura, “A physically-based nth power law model for efficient CAD implementation,” in Proc. 18th Design of Circuits and Integrated Systems Conf, Ciudad Real, Spain, Nov. 19-21, 2003, pp. 380–383.
8. A. Chatzigeorgiou, S. Nikolaidis, and I. Tsoukalas, “Estimating starting point of conduction of CMOS gates,” Electron. Lett., vol. 34, no. 17, pp. 1622–1624, 1998.