New extraction method for gate bias dependent series resistance in nanometric double gate transistors

IEEE International Conference on Microelectronic Test Structures

Volumn , Issue , 2005, Pages 69-74

  Cros, Antoine ^a,b   Harrison, Samuel ^a,c   Cerutti, Robin ^a,b   Coronel, Philippe ^a   Ghibaudo, Gérard ^b   Brut, Hugues ^a  

^a STMICROELECTRONICS   (France)

^b IMEP LAHC   (France)

^c AIX MARSEILLE UNIVERSITÉ   (France)

Author keywords

[No Author keywords available]

Indexed keywords

PARAMETER ESTIMATION; SEMICONDUCTOR DOPING; TRANSISTORS;

MOBILITY REDUCTION; SERIES RESISTANCE;

MICROELECTRONICS;

EID: 27644452547     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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