-
2
-
-
0346004030
-
-
Kluwer, Boston. MA
-
Chakrabarty, K., Iyengar, V., and Chandra, A.: 'Test resource partitioning for system-on-a-chip' (Kluwer, Boston. MA, 2002)
-
(2002)
Test Resource Partitioning for System-on-a-chip
-
-
Chakrabarty, K.1
Iyengar, V.2
Chandra, A.3
-
6
-
-
0018530675
-
Testing logic networks and design for testability
-
Williams, T.W., and Parker, K.P.: 'Testing logic networks and design for testability'. Computer, 1979, 21, pp. 9-21
-
(1979)
Computer
, vol.21
, pp. 9-21
-
-
Williams, T.W.1
Parker, K.P.2
-
7
-
-
0019633215
-
Design for autonomous test
-
McCluskev, E.J., and Bozorgui-Nesbat, S.: 'Design for autonomous test', IEEE Trans. Comput., 1981, 30, pp. 866-875
-
(1981)
IEEE Trans. Comput.
, vol.30
, pp. 866-875
-
-
McCluskev, E.J.1
Bozorgui-Nesbat, S.2
-
8
-
-
0022044251
-
Built-in self-test techniques
-
McCluskey, E.J.: 'Built-in self-test techniques', IEEE Des. Test Comput., 1985, 2, pp. 21-28
-
(1985)
IEEE Des. Test Comput.
, vol.2
, pp. 21-28
-
-
McCluskey, E.J.1
-
9
-
-
0022044647
-
Built-in self-test trends in Motorola microprocessors
-
Daniels, R.G., and Bruce, W.B.: 'Built-in self-test trends in Motorola microprocessors', IEEE Des. Test Comput., 1985, 2, pp. 64-71
-
(1985)
IEEE Des. Test Comput.
, vol.2
, pp. 64-71
-
-
Daniels, R.G.1
Bruce, W.B.2
-
10
-
-
0017007095
-
Check sum methods for test data compression
-
Haye, J.P.: 'Check sum methods for test data compression', J. Des. Autom. Fault-Toler. Comput., 1976, 1, pp. 3-7
-
(1976)
J. Des. Autom. Fault-Toler. Comput.
, vol.1
, pp. 3-7
-
-
Haye, J.P.1
-
11
-
-
0016961340
-
Transition count testing of combinational logic circuits
-
Hayes, J.P.: 'Transition count testing of combinational logic circuits', IEEE Trans. Comput., 1976, 25, pp. 613-620
-
(1976)
IEEE Trans. Comput.
, vol.25
, pp. 613-620
-
-
Hayes, J.P.1
-
12
-
-
0002553777
-
Signature analysis - A new digital field service method
-
Frohwerk, R.A.: 'Signature analysis - a new digital field service method', Hewlett-Packard J., 1977, 28, pp. 2-8
-
(1977)
Hewlett-Packard J.
, vol.28
, pp. 2-8
-
-
Frohwerk, R.A.1
-
13
-
-
0019029565
-
Syndrome-testable design of combinational circuits
-
Savir, J.: 'Syndrome-testable design of combinational circuits', IEEE Trans. Comput., 1980, 29, pp. 442-451
-
(1980)
IEEE Trans. Comput.
, vol.29
, pp. 442-451
-
-
Savir, J.1
-
14
-
-
0020708007
-
Testing by verifying Walsh coefficients
-
Susskind, A.K.: Testing by verifying Walsh coefficients', IEEE Trans. Comput., 1983, 32, pp. 198-201
-
(1983)
IEEE Trans. Comput.
, vol.32
, pp. 198-201
-
-
Susskind, A.K.1
-
15
-
-
0023980410
-
A parity bit signature for exhaustive testing
-
Akers, S.B.: 'A parity bit signature for exhaustive testing', IEEE Trans. Comput.-Aided Des., 1988, 7, pp. 333-338
-
(1988)
IEEE Trans. Comput.-Aided Des.
, vol.7
, pp. 333-338
-
-
Akers, S.B.1
-
16
-
-
0005692657
-
Multiple-output parity bit signature for exhaustive testing
-
Jone, W.-B., and Das, S.R.: 'Multiple-output parity bit signature for exhaustive testing', J. Electron. Tes., Theory Appl., 1990, 1, pp. 175-178
-
(1990)
J. Electron. Tes., Theory Appl.
, vol.1
, pp. 175-178
-
-
Jone, W.-B.1
Das, S.R.2
-
17
-
-
84947657758
-
Built-in self-testing of VLSI circuits
-
Das, S.R.: 'Built-in self-testing of VLSI circuits', IEEE Potentials, 1991, 10, pp. 23-26
-
(1991)
IEEE Potentials
, vol.10
, pp. 23-26
-
-
Das, S.R.1
-
18
-
-
0003398712
-
-
PhD Thesis, University of Michigan, Department of Computer Science and Engineering, Ann Arbor, MI
-
Chakrabarty, K.: 'Test response compaction for built-in self testing'. PhD Thesis, University of Michigan, Department of Computer Science and Engineering, Ann Arbor, MI, 1995
-
(1995)
Test Response Compaction for Built-in Self Testing
-
-
Chakrabarty, K.1
-
19
-
-
0242636492
-
Parity bit signature in response data compaction and built-in self-testing of VLSI circuits with nonexhaustive test sets
-
Das, S.R., Sudarma, M., Assaf, M.H., Petriu, E.M., Jone, W.-B., Chakrabarty, K., and Sahinoglu, M.: 'Parity bit signature in response data compaction and built-in self-testing of VLSI circuits with nonexhaustive test sets', IEEE Trans. Instrum. Meas., 2003, 52, pp. 1363-1380
-
(2003)
IEEE Trans. Instrum. Meas.
, vol.52
, pp. 1363-1380
-
-
Das, S.R.1
Sudarma, M.2
Assaf, M.H.3
Petriu, E.M.4
Jone, W.-B.5
Chakrabarty, K.6
Sahinoglu, M.7
-
20
-
-
0020951614
-
Testing computer hardware through compression in space and time
-
Saluja, K. K., and Karpovsky, M.: 'Testing computer hardware through compression in space and time'. Proc. Int. Test Conf., 1983, pp. 83-88
-
(1983)
Proc. Int. Test Conf.
, pp. 83-88
-
-
Saluja, K.K.1
Karpovsky, M.2
-
21
-
-
0022604578
-
A general scheme to optimize error masking in built-in self testing
-
Zorian, Y., and Agarwal, V.K.: 'A general scheme to optimize error masking in built-in self testing'. Proc. Int. Symp. Fault-Tolerant Computing, 1986, pp. 410-415
-
(1986)
Proc. Int. Symp. Fault-Tolerant Computing
, pp. 410-415
-
-
Zorian, Y.1
Agarwal, V.K.2
-
22
-
-
0023310935
-
Space compression method with output data modification
-
Li, Y.K., and Robinson, J.P.: 'Space compression method with output data modification', IEEE Trans. Comput.-Aided Des., 1987, 6, pp. 290-294
-
(1987)
IEEE Trans. Comput.-Aided Des.
, vol.6
, pp. 290-294
-
-
Li, Y.K.1
Robinson, J.P.2
-
23
-
-
0025252881
-
Optimal robust compression of test responses
-
Karpovsky, M., and Nagvajara, P.: 'Optimal robust compression of test responses', IEEE Trans. Comput., 1990, 39, pp. 138-141
-
(1990)
IEEE Trans. Comput.
, vol.39
, pp. 138-141
-
-
Karpovsky, M.1
Nagvajara, P.2
-
24
-
-
0000273561
-
Space compression method for built-in self-testing of VLSI circuits
-
Jone, W.-B., and Das, S.R.: 'Space compression method for built-in self-testing of VLSI circuits', Int. J. Comput. Aided VLSI Des., 1991, 3, pp. 309-322
-
(1991)
Int. J. Comput. Aided VLSI Des.
, vol.3
, pp. 309-322
-
-
Jone, W.-B.1
Das, S.R.2
-
25
-
-
0003380658
-
An improved output compaction technique for built-in self-test in VLSI circuits
-
Das, S.R., Ho, H.T., Jone, W.-B., and Nayak, A.R.: 'An improved output compaction technique for built-in self-test in VLSI circuits', Proc. Int. Conf. VLSI Design, 1994, pp. 403-407
-
(1994)
Proc. Int. Conf. VLSI Design
, pp. 403-407
-
-
Das, S.R.1
Ho, H.T.2
Jone, W.-B.3
Nayak, A.R.4
-
26
-
-
0035719333
-
Fault tolerance in systems design in VLSI using data compression under constraints of failure probabilities
-
Das, S.R., Ramamoorthy, C.V., Assaf, M.H., Petriu, E.M., and Jone, W.-B.: 'Fault tolerance in systems design in VLSI using data compression under constraints of failure probabilities', IEEE Trans. Instrum. Meas., 2001, 50, pp. 1725-1747
-
(2001)
IEEE Trans. Instrum. Meas.
, vol.50
, pp. 1725-1747
-
-
Das, S.R.1
Ramamoorthy, C.V.2
Assaf, M.H.3
Petriu, E.M.4
Jone, W.-B.5
-
27
-
-
4644301629
-
-
PhD Thesis, University of Ottawa, School of Information Technology and Engineering, Ottawa. ON, Canada
-
Assaf, M.H.: 'Digital core output test data compression architecture based on switching theory concepts'. PhD Thesis, University of Ottawa, School of Information Technology and Engineering, Ottawa. ON, Canada 2003
-
(2003)
Digital Core Output Test Data Compression Architecture Based on Switching Theory Concepts
-
-
Assaf, M.H.1
-
29
-
-
0003657590
-
-
(Seminumerical algorithms) (Addison-Wesley, Reading, MA)
-
Knuth, D.E.: 'The art of computer programming', (Seminumerical algorithms) (Addison-Wesley, Reading, MA, 1969), Vol. 2
-
(1969)
The Art of Computer Programming
, vol.2
-
-
Knuth, D.E.1
-
30
-
-
0003581572
-
On the generation of test patterns for combinational circuits
-
Department of Electrical Engineering, Virginia Polytechnic Institute and State University, Blacksburg, VA
-
Lee, H.K., and Ha, D.S.: 'On the generation of test patterns for combinational circuits'. Tech. Rep. 12-93; Department of Electrical Engineering, Virginia Polytechnic Institute and State University, Blacksburg, VA, 1993
-
(1993)
Tech. Rep.
, vol.12
, Issue.93
-
-
Lee, H.K.1
Ha, D.S.2
-
31
-
-
0026618718
-
An efficient forward fault simulation algorithm based on the parallel pattern single fault propagation
-
Lee, H.K., and Ha, D.S.: 'An efficient forward fault simulation algorithm based on the parallel pattern single fault propagation'. Proc. Int. Test Conf., 1991, pp. 946-955
-
(1991)
Proc. Int. Test Conf.
, pp. 946-955
-
-
Lee, H.K.1
Ha, D.S.2
-
32
-
-
0026618720
-
COMPACTEST: A method to generate compact test sets for combinational circuits
-
Pomeranz, I., Reddy, L.N., and Reddy, S.M.: 'COMPACTEST: a method to generate compact test sets for combinational circuits', Proc. Int. Test Conf., 1991, pp. 194-203
-
(1991)
Proc. Int. Test Conf.
, pp. 194-203
-
-
Pomeranz, I.1
Reddy, L.N.2
Reddy, S.M.3
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