A VLSI design of new memory reduction turbo code decoder

Proceedings of the IEEE International Workshop on Cellular Neural Networks and their Applications

Volumn , Issue , 2005, Pages 249-252

  Tsai, Tsung Han ^a   Lin, Cheng Hung ^a  

^a NATIONAL CENTRAL UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DECODING; FREQUENCIES; ITERATIVE METHODS; SCHEDULING; SOFTWARE PROTOTYPING; STORAGE ALLOCATION (COMPUTER); TURBO CODES;

DECODING RATES; MEMORY REDUCTION; SCHEDULING ANALYSIS; TURBO CODE DECODERS;

VLSI CIRCUITS;

EID: 27144555291     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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2. P. Robertson, E. Villebrun, P. Hoeher, "A comparison of optimal and sub-optimal MAP decoding algorithms operating in the log domain," in proc. IEEE Int. Conf. Communications, 1995, pp. 1009-1013.
3. A. J. Viterbi, "An intuitive justification and simplified implementation of the MAP decoder for convolutional codes," IEEE J. Selected Area in Communication, vol. 16, pp. 260-264, Feb. 1998.
4. E. Boutillon, W. J. Gross, and P. G. Gulak, "VLSI architectures for the MAP algorithm," IEEE Trans. Communications, vol. 51, pp. 175-185, Feb. 2003.
5. rd Generation Partnership Project, 3GPP TS25.212 v5.1.0, 2002.T.
6. T.-H. Tsai and C.-H. Lin, "A Low Complexity Channel Estimation Algorithm and Architecture Design in Turbo Codes with Early Termination Techniques," in Proc. IEEE 6th CAS Symp. Frontiers of Mobile and Wireless Commun., vol. 1, pp. 213-216, May 2004.
7. A. Raghupathy, and K. J. R. Liu, "A transformation for computational latency reduction in turbo-MAP decoding," in Proc. ISCAS '99, vol. 4, pp. 402-405, Jul 1999.